Searched refs:pll_clk (Results 1 – 8 of 8) sorted by relevance
| /drivers/clk/exynos/ |
| A D | clk-pll.c | 102 const struct samsung_pll_clock *pll_clk) in _samsung_clk_register_pll() argument
113 pll->con_reg = base + pll_clk->con_offset; in _samsung_clk_register_pll()
114 pll->type = pll_clk->type; in _samsung_clk_register_pll()
116 clk->flags = pll_clk->flags; in _samsung_clk_register_pll()
118 switch (pll_clk->type) { in _samsung_clk_register_pll()
130 ret = clk_register(clk, drv_name, pll_clk->name, pll_clk->parent_name); in _samsung_clk_register_pll()
147 const struct samsung_pll_clock *pll_clk; in samsung_clk_register_pll() local
150 pll_clk = &clk_list[cnt]; in samsung_clk_register_pll()
151 clk = _samsung_clk_register_pll(base, pll_clk); in samsung_clk_register_pll()
152 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, pll_clk->id); in samsung_clk_register_pll()
|
| /drivers/clk/imx/ |
| A D | clk-fracn-gppll.c | 338 const struct imx_fracn_gppll_clk *pll_clk, in _imx_clk_fracn_gppll() argument
350 pll->rate_table = pll_clk->rate_table; in _imx_clk_fracn_gppll()
351 pll->rate_count = pll_clk->rate_count; in _imx_clk_fracn_gppll()
368 const struct imx_fracn_gppll_clk *pll_clk) in imx_clk_fracn_gppll() argument
370 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN); in imx_clk_fracn_gppll()
375 const struct imx_fracn_gppll_clk *pll_clk) in imx_clk_fracn_gppll_integer() argument
377 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER); in imx_clk_fracn_gppll_integer()
|
| A D | clk-pll14xx.c | 391 const struct imx_pll14xx_clk *pll_clk) in imx_clk_pll14xx() argument
402 switch (pll_clk->type) { in imx_clk_pll14xx()
417 pll->type = pll_clk->type; in imx_clk_pll14xx()
418 pll->rate_table = pll_clk->rate_table; in imx_clk_pll14xx()
419 pll->rate_count = pll_clk->rate_count; in imx_clk_pll14xx()
|
| A D | clk.h | 69 const struct imx_fracn_gppll_clk *pll_clk);
72 const struct imx_fracn_gppll_clk *pll_clk);
79 const struct imx_pll14xx_clk *pll_clk);
|
| /drivers/clk/starfive/ |
| A D | clk-jh7110-pll.c | 324 const struct starfive_pllx_clk *pll_clk) in starfive_jh7110_pll() argument
330 if (!pll_clk || !base || !sysreg) in starfive_jh7110_pll()
339 pll->type = pll_clk->type; in starfive_jh7110_pll()
340 pll->offset = pll_clk->offset; in starfive_jh7110_pll()
341 pll->rate_table = pll_clk->rate_table; in starfive_jh7110_pll()
342 pll->rate_count = pll_clk->rate_count; in starfive_jh7110_pll()
|
| /drivers/spi/ |
| A D | mtk_spim.c | 417 u32 pll_clk, sck_l, sck_h, clk_count, reg; in mtk_spim_transfer_wait() local
426 pll_clk = priv->pll_clk_rate; in mtk_spim_transfer_wait()
429 do_div(pll_clk, sck_l + sck_h + 2); in mtk_spim_transfer_wait()
431 us = CLK_TO_US(pll_clk, clk_count * 8); in mtk_spim_transfer_wait()
|
| /drivers/pinctrl/qcom/ |
| A D | pinctrl-sa8775p.c | 298 MSM_PIN_FUNCTION(pll_clk),
438 [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _),
|
| /drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-dsidphy.c | 220 struct clk *pll_clk; member
|
Completed in 20 milliseconds