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Searched refs:pll_rate (Results 1 – 15 of 15) sorted by relevance

/drivers/clk/rockchip/
A Dclk_rv1108.c150 ulong pll_rate; in rv1108_mac_set_clk() local
156 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
162 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
169 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
175 u32 pll_rate; in rv1108_sfc_set_clk() local
183 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
190 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
513 u32 pll_rate; in rv1108_mmc_set_clk() local
526 pll_rate = OSC_HZ; in rv1108_mmc_set_clk()
529 div = DIV_ROUND_UP(pll_rate / 2, rate); in rv1108_mmc_set_clk()
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A Dclk_rk3368.c164 u32 pll_rate; in rk3368_mmc_get_clk() local
183 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
186 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
189 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
196 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
329 ulong pll_rate; in rk3368_gmac_set_clk() local
334 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
337 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
342 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
349 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
A Dclk_rk3576.c1171 if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3576_dclk_vop_set_clk()
1200 pll_rate = 0; in rk3576_dclk_vop_set_clk()
1203 pll_rate = 0; in rk3576_dclk_vop_set_clk()
1206 pll_rate = 0; in rk3576_dclk_vop_set_clk()
1216 now = pll_rate / div; in rk3576_dclk_vop_set_clk()
1298 pll_rate = 0; in rk3576_clk_csihost_set_clk()
1301 pll_rate = 0; in rk3576_clk_csihost_set_clk()
1304 pll_rate = 0; in rk3576_clk_csihost_set_clk()
1317 now = pll_rate / div; in rk3576_clk_csihost_set_clk()
1443 pll_rate = 0; in rk3576_dclk_ebc_set_clk()
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A Dclk_rk3308.c246 ulong pll_rate; in rk3308_mac_set_clk() local
256 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
263 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
268 return DIV_TO_RATE(pll_rate, div); in rk3308_mac_set_clk()
595 ulong pll_rate, now, best_rate = 0; in rk3308_vop_set_clk() local
601 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
604 pll_rate = priv->vpll0_hz; in rk3308_vop_set_clk()
607 pll_rate = priv->vpll1_hz; in rk3308_vop_set_clk()
614 div = DIV_ROUND_UP(pll_rate, hz); in rk3308_vop_set_clk()
617 now = pll_rate / div; in rk3308_vop_set_clk()
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A Dclk_rk322x.c257 ulong pll_rate; in rk322x_mac_set_clk() local
261 pll_rate = GPLL_HZ; in rk322x_mac_set_clk()
266 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rk322x_mac_set_clk()
273 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
A Dclk_rk3288.c316 ulong pll_rate; in rockchip_mac_set_clk() local
321 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
324 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
326 pll_rate = NPLL_HZ; in rockchip_mac_set_clk()
328 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
335 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
A Dclk_rk3588.c1096 ulong pll_rate, now, best_rate = 0; in rk3588_dclk_vop_set_clk() local
1141 pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1143 if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3588_dclk_vop_set_clk()
1144 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1162 pll_rate = priv->gpll_hz; in rk3588_dclk_vop_set_clk()
1165 pll_rate = priv->cpll_hz; in rk3588_dclk_vop_set_clk()
1168 pll_rate = priv->aupll_hz; in rk3588_dclk_vop_set_clk()
1171 pll_rate = 0; in rk3588_dclk_vop_set_clk()
1178 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1181 now = pll_rate / div; in rk3588_dclk_vop_set_clk()
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A Dclk_rk3328.c427 ulong pll_rate; in rk3328_gmac2io_set_clk() local
431 pll_rate = GPLL_HZ; in rk3328_gmac2io_set_clk()
433 pll_rate = CPLL_HZ; in rk3328_gmac2io_set_clk()
435 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
442 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
A Dclk_px30.c1085 ulong pll_rate; in px30_mac_set_clk() local
1089 pll_rate = px30_clk_get_pll_rate(priv, CPLL); in px30_mac_set_clk()
1091 pll_rate = px30_clk_get_pll_rate(priv, NPLL); in px30_mac_set_clk()
1093 pll_rate = priv->gpll_hz; in px30_mac_set_clk()
1099 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
1104 return DIV_TO_RATE(pll_rate, div); in px30_mac_set_clk()
1596 ulong pll_rate; in px30_pmu_uart0_get_clk() local
1607 pll_rate = px30_pmuclk_get_gpll_rate(priv); in px30_pmu_uart0_get_clk()
1610 pll_rate = OSC_HZ; in px30_pmu_uart0_get_clk()
1619 clk = DIV_TO_RATE(pll_rate, clk_div_con); in px30_pmu_uart0_get_clk()
A Dclk_rv1126.c1193 ulong pll_rate, now, best_rate = 0; in rv1126_dclk_vop_set_clk() local
1199 pll_rate = priv->gpll_hz; in rv1126_dclk_vop_set_clk()
1202 pll_rate = priv->cpll_hz; in rv1126_dclk_vop_set_clk()
1209 div = DIV_ROUND_UP(pll_rate, rate); in rv1126_dclk_vop_set_clk()
1212 now = pll_rate / div; in rv1126_dclk_vop_set_clk()
1219 pll_rate, best_rate, best_div, best_sel); in rv1126_dclk_vop_set_clk()
A Dclk_rk3568.c1795 ulong pll_rate, now, best_rate = 0; in rk3568_dclk_vop_set_clk() local
1834 pll_rate = priv->gpll_hz; in rk3568_dclk_vop_set_clk()
1837 pll_rate = priv->cpll_hz; in rk3568_dclk_vop_set_clk()
1844 div = DIV_ROUND_UP(pll_rate, rate); in rk3568_dclk_vop_set_clk()
1847 now = pll_rate / div; in rk3568_dclk_vop_set_clk()
1854 pll_rate, best_rate, best_div, best_sel); in rk3568_dclk_vop_set_clk()
/drivers/clk/
A Dclk-hsdk-cgu.c145 const u32 pll_rate[MAX_FREQ_VARIATIONS]; member
597 ulong pll_rate; in common_div_clk_set() local
601 pll_rate = pll_get(sclk); in common_div_clk_set()
620 if (cfg->pll_rate[freq_idx] < pll_rate) in common_div_clk_set()
621 ret = pll_set(sclk, cfg->pll_rate[freq_idx]); in common_div_clk_set()
630 if (cfg->pll_rate[freq_idx] >= pll_rate) in common_div_clk_set()
631 ret = pll_set(sclk, cfg->pll_rate[freq_idx]); in common_div_clk_set()
A Dclk_zynq.c290 ulong pll_rate, in zynq_clk_calc_peripheral_two_divs() argument
300 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynq_clk_calc_peripheral_two_divs()
321 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
328 pll_rate = zynq_clk_get_pll_rate(priv, pll); in zynq_clk_set_peripheral_rate()
332 new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, in zynq_clk_set_peripheral_rate()
336 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynq_clk_set_peripheral_rate()
A Dclk_zynqmp.c615 ulong pll_rate, in zynqmp_clk_calc_peripheral_two_divs() argument
625 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynqmp_clk_calc_peripheral_two_divs()
646 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
660 pll_rate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_set_peripheral_rate()
661 if (IS_ERR_VALUE(pll_rate)) in zynqmp_clk_set_peripheral_rate()
662 return pll_rate; in zynqmp_clk_set_peripheral_rate()
667 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, in zynqmp_clk_set_peripheral_rate()
671 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynqmp_clk_set_peripheral_rate()
/drivers/clk/at91/
A Dclk-sam9x60-pll.c144 ulong pll_rate; in sam9x60_frac_pll_get_rate() local
154 pll_rate = (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22)); in sam9x60_frac_pll_get_rate()
157 pll_rate >>= 1; in sam9x60_frac_pll_get_rate()
159 return pll_rate; in sam9x60_frac_pll_get_rate()

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