| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_pbs.c | 86 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
99 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
175 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
334 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
349 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
372 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
399 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
460 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
477 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
626 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
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| A D | ddr3_training_hw_algo.c | 184 for (pup = 0; in ddr3_tip_vref()
185 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
212 if_id, pup, in ddr3_tip_vref()
261 for (pup = 0; in ddr3_tip_vref()
262 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
275 for (pup = 0; in ddr3_tip_vref()
276 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
366 [pup] in ddr3_tip_vref()
406 [pup] in ddr3_tip_vref()
603 for (pup = 0; in ddr3_tip_vref()
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| A D | ddr3_debug.c | 1110 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1127 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1157 pup, in ddr3_tip_run_sweep_test()
1175 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1194 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1250 for (pup = start_pup; pup <= end_pup; pup++) in ddr3_tip_run_leveling_sweep_test()
1272 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_leveling_sweep_test()
1300 pup, in ddr3_tip_run_leveling_sweep_test()
1360 pup, in ddr3_tip_run_leveling_sweep_test()
1375 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_leveling_sweep_test()
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_pbs.c | 90 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
103 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
179 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
338 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
353 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
376 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
403 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
464 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
481 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
630 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
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| A D | ddr3_training_hw_algo.c | 188 for (pup = 0; in ddr3_tip_vref()
189 pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_vref()
216 if_id, pup, in ddr3_tip_vref()
265 for (pup = 0; in ddr3_tip_vref()
266 pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_vref()
279 for (pup = 0; in ddr3_tip_vref()
280 pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_vref()
370 [pup] in ddr3_tip_vref()
410 [pup] in ddr3_tip_vref()
607 for (pup = 0; in ddr3_tip_vref()
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| A D | ddr3_debug.c | 1304 u32 pup = 0, start_pup = 0, end_pup = 0; in ddr3_tip_run_sweep_test() local
1335 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1336 ctrl_sweepres[adll][if_id][pup] = in ddr3_tip_run_sweep_test()
1353 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1359 pup_access, pup, DDR_PHY_DATA, in ddr3_tip_run_sweep_test()
1371 ctrl_sweepres[adll][if_id][pup] in ddr3_tip_run_sweep_test()
1380 pup, in ddr3_tip_run_sweep_test()
1386 + pup])); in ddr3_tip_run_sweep_test()
1396 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1415 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
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| /drivers/ddr/marvell/axp/ |
| A D | ddr3_dqs.c | 326 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
342 for (pup = 0; pup < max_pup; pup++) in ddr3_find_adll_limits()
345 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
367 for (pup = 0; pup < max_pup; pup++) in ddr3_find_adll_limits()
377 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
391 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
433 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
772 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
792 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
971 for (pup = 0; pup < max_pup; pup++) in ddr3_special_pattern_i_search()
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| A D | ddr3_pbs.c | 124 for (pup = 0; pup < pups; pup++) { in ddr3_pbs_tx()
293 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
322 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
337 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
344 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
370 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_tx()
451 for (pup = 0; pup < cur_max_pup; pup++) in ddr3_tx_shift_dqs_adll_step_before_fail()
504 for (pup = 0; pup < cur_max_pup; pup++) in ddr3_tx_shift_dqs_adll_step_before_fail()
567 for (pup = 0; pup < pups; pup++) { in ddr3_pbs_rx()
853 for (pup = 0; pup < max_pup; pup++) { in ddr3_pbs_rx()
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| A D | ddr3_write_leveling.c | 293 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_wl_supplement()
396 pup = (ecc) ? max_pup_num : pup; in ddr3_wl_supplement()
409 for (pup = 0; pup < dram_info->num_of_std_pups; pup++) in ddr3_wl_supplement()
433 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_wl_supplement()
489 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_hw_reg_dimm()
774 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_write_leveling_sw()
905 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1104 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1263 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1302 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
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| A D | ddr3_read_leveling.c | 421 pup++) in ddr3_read_leveling_single_cs_rl_mode()
466 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
576 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
604 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
677 for (pup = 0; pup < in ddr3_read_leveling_single_cs_rl_mode()
688 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
730 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
775 pup++) in ddr3_read_leveling_single_cs_window_mode()
819 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
1091 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
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| A D | ddr3_sdram.c | 106 *pup |= (1 << (uk + (PUP_NUM_32BIT * in compare_pattern_v1()
142 *pup |= (1 << (uk % PUP_NUM_16BIT)); in compare_pattern_v2()
224 u32 pup = 0; in ddr3_sdram_dm_compare() local
257 *new_locked_pup |= pup; in ddr3_sdram_dm_compare()
290 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
339 for (pup = 0; pup < PUP_NUM_32BIT; pup++) { in ddr3_sdram_pbs_compare()
340 val = CMP_BYTE_SHIFT * pup; in ddr3_sdram_pbs_compare()
348 tmp_pup = (pup + PUP_NUM_32BIT * in ddr3_sdram_pbs_compare()
351 tmp_pup = (pup % PUP_NUM_16BIT); in ddr3_sdram_pbs_compare()
404 for (pup = 0; pup < max_pup; pup++) { in ddr3_sdram_pbs_compare()
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| A D | ddr3_hw_training.c | 552 if (pup == PUP_BC) in ddr3_write_pup_reg()
576 if (pup == PUP_BC) in ddr3_write_pup_reg()
698 u32 val, pup, tmp_cs, cs, i, dq; in ddr3_save_training() local
719 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
720 pup++) { in ddr3_save_training()
723 pup = ECC_PUP; in ddr3_save_training()
731 mode_config[i], CS0, pup); in ddr3_save_training()
744 pup); in ddr3_save_training()
753 mode_config[i], cs, pup); in ddr3_save_training()
1049 u32 pup, reg, phase; in ddr3_get_min_max_rl_phase() local
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| A D | ddr3_hw_training.h | 326 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
327 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
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| /drivers/power/domain/ |
| A D | imx8m-power-domain.c | 119 u16 pup; member
156 .pup = GPC_PU_PGC_SW_PUP_REQ,
327 .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
362 setbits_le32(base + regs->pup, domain->bits.pxx); in imx8m_power_domain_on()
368 ret = wait_for_bit_le32(base + regs->pup, domain->bits.pxx, in imx8m_power_domain_on()
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