| /drivers/ddr/marvell/axp/ |
| A D | ddr3_dfs.c | 70 u32 reg; in wait_refresh_op_complete() local
184 } while (reg); in ddr3_dfs_high_2_low()
271 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
279 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
298 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
313 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
332 reg = 0x000000FF; in ddr3_dfs_high_2_low()
422 } while (reg); in ddr3_dfs_high_2_low()
506 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
1117 } while (reg); in ddr3_dfs_low_2_high()
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| A D | ddr3_write_leveling.c | 115 reg = in ddr3_write_leveling_hw()
126 reg = in ddr3_write_leveling_hw()
251 reg = in ddr3_wl_supplement()
255 reg |= in ddr3_wl_supplement()
400 reg = in ddr3_wl_supplement()
538 reg = in ddr3_write_leveling_hw_reg_dimm()
562 reg = in ddr3_write_leveling_hw_reg_dimm()
729 reg = in ddr3_write_leveling_sw()
737 reg = in ddr3_write_leveling_sw()
963 reg = in ddr3_write_leveling_sw_reg_dimm()
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| A D | ddr3_hw_training.c | 84 u32 freq, reg; in ddr3_hw_training() local
135 reg = (((reg >> 1) & 0xE) | (reg & 0x1)) & 0xF; in ddr3_hw_training()
550 u32 reg = 0; in ddr3_write_pup_reg() local
574 reg = 0; in ddr3_write_pup_reg()
591 } while (reg); in ddr3_write_pup_reg()
600 u32 reg; in ddr3_read_pup_reg() local
622 u32 reg; in ddr3_load_patterns() local
916 u32 freq, reg; in ddr3_training_suspend_resume() local
1070 u32 reg, mask; in ddr3_odt_activate() local
1077 reg |= mask; in ddr3_odt_activate()
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| A D | ddr3_init.c | 72 printf("0x%08x = 0x%08x\n", reg, reg_read(reg)); in debug_print_reg()
141 u32 ui, reg, cs; in ddr3_restore_and_set_final_windows() local
230 reg = 0; in ddr3_save_and_set_training_windows()
236 reg = 0x0E00; in ddr3_save_and_set_training_windows()
252 reg); in ddr3_save_and_set_training_windows()
255 reg); in ddr3_save_and_set_training_windows()
355 u32 reg = 0; in ddr3_init_main() local
597 } while (reg); in ddr3_init_main()
786 u32 reg; in ddr3_static_training_init() local
821 u32 reg, tmp; in ddr3_get_static_mc_value() local
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| A D | ddr3_spd.c | 709 reg = ((((reg >> 1) & 0xE)) | (reg & 0x1)) & 0xF;
779 reg |= tmp;
797 reg = 0x0;
946 reg = 0xF00;
991 reg = cs_ena;
1046 reg = 0;
1057 reg = 0;
1141 reg = 0;
1157 reg = cs_ena;
1210 reg |= 0x8;
[all …]
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| /drivers/video/exynos/ |
| A D | exynos_dp_lowlevel.c | 23 unsigned int reg; in exynos_dp_enable_video_input() local
40 unsigned int reg; in exynos_dp_enable_video_bist() local
56 unsigned int reg; in exynos_dp_enable_video_mute() local
70 unsigned int reg; in exynos_dp_init_analog_param() local
196 reg |= AUX_PD; in exynos_dp_set_analog_power_down()
325 reg = INT_HPD; in exynos_dp_init_hpd()
432 reg |= AUX_EN; in exynos_dp_start_aux_transaction()
480 reg = BUF_CLR; in exynos_dp_write_byte_to_dpcd()
521 reg = BUF_CLR; in exynos_dp_read_byte_from_dpcd()
565 reg = BUF_CLR; in exynos_dp_write_bytes_to_dpcd()
[all …]
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| A D | exynos_mipi_dsi_lowlevel.c | 20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
27 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
41 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
66 reg |= mode; in exynos_mipi_dsi_set_interrupt_mask()
68 reg &= ~mode; in exynos_mipi_dsi_set_interrupt_mask()
76 unsigned int reg; in exynos_mipi_dsi_init_fifo_pointer() local
84 reg |= cfg; in exynos_mipi_dsi_init_fifo_pointer()
104 unsigned int reg; in exynos_mipi_dsi_set_main_disp_resol() local
123 unsigned int reg; in exynos_mipi_dsi_set_main_disp_vporch() local
141 unsigned int reg; in exynos_mipi_dsi_set_main_disp_hporch() local
[all …]
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| /drivers/watchdog/ |
| A D | orion_wdt.c | 29 void __iomem *reg; member
62 u32 reg; in orion_wdt_start() local
67 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
69 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
76 reg = readl(priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
78 writel(reg, priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
81 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
83 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
100 u32 reg; in orion_wdt_stop() local
112 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_stop()
[all …]
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| /drivers/phy/ |
| A D | phy-exynos-usbdrd.c | 105 *reg = EXYNOS5_FSEL_9MHZ6; in exynos_rate_to_clk()
108 *reg = EXYNOS5_FSEL_10MHZ; in exynos_rate_to_clk()
111 *reg = EXYNOS5_FSEL_12MHZ; in exynos_rate_to_clk()
117 *reg = EXYNOS5_FSEL_20MHZ; in exynos_rate_to_clk()
139 u32 reg; in exynos850_usbdrd_utmi_init() local
152 reg |= CLKRST_PHY_SW_RST; in exynos850_usbdrd_utmi_init()
180 reg &= ~SSPPLLCTL_FSEL; in exynos850_usbdrd_utmi_init()
206 reg &= ~HSP_TEST_SIDDQ; in exynos850_usbdrd_utmi_init()
218 reg &= ~HSP_FSV_OUT_EN; in exynos850_usbdrd_utmi_init()
226 u32 reg; in exynos850_usbdrd_utmi_exit() local
[all …]
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| /drivers/spi/ |
| A D | cadence_qspi_apb.c | 47 unsigned int reg; in cadence_qspi_apb_controller_enable() local
55 unsigned int reg; in cadence_qspi_apb_controller_disable() local
63 unsigned int reg; in cadence_qspi_apb_dac_mode_enable() local
180 unsigned int reg; in cadence_qspi_apb_readdata_capture() local
204 unsigned int reg; in cadence_qspi_apb_config_baudrate_div() local
233 unsigned int reg; in cadence_qspi_apb_set_clk_mode() local
252 unsigned int reg; in cadence_qspi_apb_chipselect() local
330 unsigned reg; in cadence_qspi_apb_controller_init() local
680 u32 reg; in cadence_qspi_wait_for_data() local
684 if (reg) in cadence_qspi_wait_for_data()
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| /drivers/i2c/ |
| A D | npcm_i2c.c | 117 struct npcm_i2c_regs *reg = bus->reg; in npcm_dump_regs() local
128 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_check_sda() local
159 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_send_start() local
182 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_send_stop() local
213 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_reset() local
244 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_recovery() local
287 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_send_address() local
324 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_read_bytes() local
383 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_send_bytes() local
413 struct npcm_i2c_regs *reg = bus->reg; in npcm_i2c_read() local
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| /drivers/clk/at91/ |
| A D | clk-main.c | 35 void __iomem *reg; member
62 void __iomem *reg = main_rc->reg; in main_rc_enable() local
86 struct reg *reg = main_rc->reg; in main_rc_disable() local
120 main_rc->reg = reg; in at91_clk_main_rc()
143 void __iomem *reg = main->reg; in clk_main_osc_enable() local
170 void __iomem *reg = main->reg; in clk_main_osc_disable() local
206 main->reg = reg; in at91_clk_main_osc()
272 main->reg = reg; in at91_clk_rm9200_main()
304 void __iomem *reg = main->reg; in clk_sam9x5_main_enable() local
317 void __iomem *reg = main->reg; in clk_sam9x5_main_set_parent() local
[all …]
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| /drivers/video/imx/ |
| A D | ipu_disp.c | 184 u32 reg; in ipu_di_data_wave_config() local
193 u32 reg; in ipu_di_data_pin_config() local
212 u32 reg; in ipu_di_sync_config() local
241 u32 reg; in ipu_dc_map_config() local
264 u32 reg; in ipu_dc_write_tmpl() local
267 reg = sync; in ipu_dc_write_tmpl()
282 u32 reg; in ipu_dc_link_event() local
383 u32 reg; in ipu_dp_csc_setup() local
533 u32 reg = 0; in ipu_dc_init() local
560 reg = 0x2; in ipu_dc_init()
[all …]
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| /drivers/clk/starfive/ |
| A D | clk-jh7110.c | 35 void __iomem *reg; member
145 mux->reg = reg + offset; in starfive_clk_composite()
159 gate->reg = reg + offset; in starfive_clk_composite()
169 div->reg = reg + offset; in starfive_clk_composite()
271 starfive_clk_gate(priv->reg, in jh7110_syscrg_init()
275 starfive_clk_gate(priv->reg, in jh7110_syscrg_init()
283 starfive_clk_gate(priv->reg, in jh7110_syscrg_init()
287 starfive_clk_gate(priv->reg, in jh7110_syscrg_init()
291 starfive_clk_gate(priv->reg, in jh7110_syscrg_init()
304 starfive_clk_gate(priv->reg, in jh7110_syscrg_init()
[all …]
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| /drivers/pinctrl/rockchip/ |
| A D | pinctrl-rk3576.c | 19 int reg, mask; in rk3576_set_mux() local
26 reg += 0x4; in rk3576_set_mux()
53 int *reg, u8 *bit) in rk3576_calc_drv_reg_and_bit() argument
75 *reg = 0; in rk3576_calc_drv_reg_and_bit()
88 int reg; in rk3576_set_drive() local
116 int *reg, u8 *bit) in rk3576_calc_pull_reg_and_bit() argument
138 *reg = 0; in rk3576_calc_pull_reg_and_bit()
151 int reg, ret; in rk3576_set_pull() local
188 int *reg, u8 *bit) in rk3576_calc_schmitt_reg_and_bit() argument
210 *reg = 0; in rk3576_calc_schmitt_reg_and_bit()
[all …]
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| A D | pinctrl-rv1108.c | 19 .reg = 0x418,
25 .reg = 0x418,
31 .reg = 0x418,
37 .reg = 0x418,
43 .reg = 0x418,
49 .reg = 0x418,
55 .reg = 0x418,
61 .reg = 0x418,
67 .reg = 0x41c,
73 .reg = 0x41c,
[all …]
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| A D | pinctrl-rk3528.c | 19 int reg, mask; in rk3528_set_mux() local
26 reg += 0x4; in rk3528_set_mux()
47 int *reg, u8 *bit) in rk3528_calc_drv_reg_and_bit() argument
64 *reg = 0; in rk3528_calc_drv_reg_and_bit()
77 int reg; in rk3528_set_drive() local
102 int *reg, u8 *bit) in rk3528_calc_pull_reg_and_bit() argument
119 *reg = 0; in rk3528_calc_pull_reg_and_bit()
132 int reg, ret; in rk3528_set_pull() local
166 int *reg, u8 *bit) in rk3528_calc_schmitt_reg_and_bit() argument
183 *reg = 0; in rk3528_calc_schmitt_reg_and_bit()
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| A D | pinctrl-rk3308.c | 19 .reg = 0x28,
25 .reg = 0x2c,
31 .reg = 0x30,
37 .reg = 0x30,
43 .reg = 0x30,
49 .reg = 0x34,
55 .reg = 0x34,
61 .reg = 0x34,
67 .reg = 0x68,
73 .reg = 0x68,
[all …]
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| /drivers/clk/imx/ |
| A D | clk.h | 118 void __iomem *reg, u8 shift) in imx_clk_gate4() argument
122 reg, shift, 0x3, 0, NULL); in imx_clk_gate4()
131 reg, shift, 0x3, 0, NULL); in imx_clk_gate4_flags()
147 reg, shift, width, 0); in imx_clk_divider()
156 reg, shift, width, 0); in imx_clk_busy_divider()
165 reg, shift, width, 0); in imx_clk_divider2()
169 void __iomem *reg, u8 idx);
192 reg, shift, width, 0); in imx_clk_mux2_flags()
220 reg, shift, width, 0); in imx_clk_mux2()
245 reg, shift, 0, NULL); in imx_clk_gate3()
[all …]
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| /drivers/pci/ |
| A D | pci-aardvark.c | 171 writel(val, pcie->base + reg); in advk_writel()
176 return readl(pcie->base + reg); in advk_readl()
274 uint reg; in pcie_advk_check_pio_status() local
360 uint reg; in pcie_advk_read_config() local
486 offset, size, reg); in pcie_advk_read_config()
544 uint reg; in pcie_advk_write_config() local
757 u32 reg; in pcie_advk_setup_hw() local
766 reg |= ADVK_GLOBAL_CTRL0_IS_RC; in pcie_advk_setup_hw()
801 reg &= ~0xffffff00; in pcie_advk_setup_hw()
815 reg &= ~PCI_EXP_DEVCTL_READRQ; in pcie_advk_setup_hw()
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| /drivers/net/phy/ |
| A D | marvell.c | 302 int reg; in m88e1111s_config() local
392 u16 reg, mask; in m88e151x_phy_writebits() local
401 reg &= ~mask; in m88e151x_phy_writebits()
409 u16 reg; in m88e151x_config() local
549 int reg; in m88e1145_config() local
622 u16 reg; in m88e1310_config() local
627 reg = (reg & ~0xf) | 0x1; in m88e1310_config()
633 reg = (reg & 0x77ff) | 0x0880; in m88e1310_config()
639 reg |= 0x0030; in m88e1310_config()
656 u16 reg; in m88e1680_config() local
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| /drivers/clk/ |
| A D | clk-gate.c | 56 u32 reg; in clk_gate_endisable() local
66 reg = gate->io_gate_val; in clk_gate_endisable()
68 reg = readl(gate->reg); in clk_gate_endisable()
77 writel(reg, gate->reg); in clk_gate_endisable()
97 u32 reg; in clk_gate_is_enabled() local
100 reg = gate->io_gate_val; in clk_gate_is_enabled()
102 reg = readl(gate->reg); in clk_gate_is_enabled()
107 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
109 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
111 return reg ? 1 : 0; in clk_gate_is_enabled()
[all …]
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| /drivers/mtd/nand/raw/ |
| A D | tegra_nand.c | 95 struct nand_ctlr *reg; member
103 struct nand_ctlr *reg; member
186 unsigned int reg; in read_buf() local
194 &info->reg->command); in read_buf()
197 reg = readl(&info->reg->resp); in read_buf()
309 &info->reg->command); in nand_command()
334 &info->reg->command); in nand_command()
343 &info->reg->command); in nand_command()
348 &info->reg->command); in nand_command()
461 ®->dma_mst_ctrl); in stop_command()
[all …]
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| A D | arasan_nfc.c | 28 struct nand_regs *reg; member
434 &info->reg->intsts_enr); in arasan_nand_read_page()
437 &info->reg->intsts_reg); in arasan_nand_read_page()
606 &info->reg->intsts_enr); in arasan_nand_write_page_hwecc()
609 &info->reg->intsts_reg); in arasan_nand_write_page_hwecc()
647 &info->reg->intsts_enr); in arasan_nand_reset()
667 &info->reg->intsts_enr); in arasan_nand_reset()
670 &info->reg->intsts_reg); in arasan_nand_reset()
715 &info->reg->intsts_enr); in arasan_nand_send_wrcmd()
780 &info->reg->intsts_enr); in arasan_nand_write_buf()
[all …]
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| /drivers/mmc/ |
| A D | tegra_mmc.c | 30 struct tegra_mmc *reg; member
68 writeb(pwr, &priv->reg->pwrcon); in tegra_mmc_set_power()
74 writeb(pwr, &priv->reg->pwrcon); in tegra_mmc_set_power()
95 ctrl = readb(&priv->reg->hostctl); in tegra_mmc_prepare_data()
98 writeb(ctrl, &priv->reg->hostctl); in tegra_mmc_prepare_data()
129 writew(mode, &priv->reg->trnmod); in tegra_mmc_set_transfer_mode()
256 (&priv->reg->rspreg3 - i); in tegra_mmc_send_cmd_bounced()
269 if (readl(&priv->reg->prnsts) in tegra_mmc_send_cmd_bounced()
404 writew(0, &priv->reg->clkcon); in tegra_mmc_change_clock()
483 priv->reg, id); in tegra_mmc_pad_init()
[all …]
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