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Searched refs:reg_bit_set (Results 1 – 10 of 10) sorted by relevance

/drivers/ddr/marvell/axp/
A Dxor.c202 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
313 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_transfer()
404 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_cmd_set()
410 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_cmd_set()
416 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_cmd_set()
422 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_cmd_set()
A Dddr3_init.c388 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
389 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
391 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
393 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
A Dddr3_init.h131 static inline void reg_bit_set(u32 addr, u32 mask) in reg_bit_set() function
/drivers/ddr/marvell/a38x/
A Dxor.c216 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
305 reg_bit_set(XOR_ACTIVATION_REG in mv_xor_command_set()
311 reg_bit_set(XOR_ACTIVATION_REG in mv_xor_command_set()
318 reg_bit_set(XOR_ACTIVATION_REG in mv_xor_command_set()
324 reg_bit_set(XOR_ACTIVATION_REG in mv_xor_command_set()
460 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_transfer()
A Dmv_ddr_plat.c276 reg_bit_set(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK); in ddr3_ctrl_get_junc_temp()
1341 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1342 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1345 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1348 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1361 reg_bit_set(SDRAM_INIT_CTRL_REG, in mv_ddr_pre_training_soc_config()
A Dddr_ml_wrapper.h134 static inline void reg_bit_set(u32 addr, u32 mask) in reg_bit_set() function
/drivers/gpio/
A Dgpio-aspeed-sgpio.c84 void (*reg_bit_set)(struct aspeed_sgpio_priv *gpio, unsigned int offset, member
146 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, value); in aspeed_sgpio_set_value()
207 .reg_bit_set = aspeed_g4_reg_bit_set,
/drivers/ddr/marvell/a38x/old/
A Dddr3_init.c308 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in ddr3_init()
310 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in ddr3_init()
322 reg_bit_set(REG_SDRAM_INIT_CTRL_ADDR, in ddr3_init()
A Dddr3_a38x.c210 reg_bit_set(TSEN_CONF_REG, TSEN_CONF_RST_MASK); in ddr3_ctrl_get_junc_temp()
A Dddr3_init.h395 static inline void reg_bit_set(u32 addr, u32 mask) in reg_bit_set() function

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