Searched refs:reg_ctrl (Results 1 – 3 of 3) sorted by relevance
| /drivers/spi/ |
| A D | mxc_spi.c | 225 s32 reg_ctrl, reg_config; in spi_cfg_mxc() local
237 reg_ctrl = MXC_CSPICTRL_MODE_MASK; in spi_cfg_mxc()
238 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
239 reg_ctrl |= MXC_CSPICTRL_EN; in spi_cfg_mxc()
240 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
260 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | in spi_cfg_mxc()
262 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | in spi_cfg_mxc()
264 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | in spi_cfg_mxc()
293 debug("reg_ctrl = 0x%x\n", reg_ctrl); in spi_cfg_mxc()
294 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
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| /drivers/net/ |
| A D | e1000.c | 1727 uint32_t reg_ctrl, reg_ctrl_ext; in e1000_initialize_hardware_bits() local
1776 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1777 reg_ctrl &= ~(1 << 29); in e1000_initialize_hardware_bits()
1780 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
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| /drivers/video/sunxi/ |
| A D | sunxi_display.c | 530 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); in sunxi_composer_enable()
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