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Searched refs:reg_data (Results 1 – 25 of 32) sorted by relevance

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/drivers/phy/marvell/
A Dcomphy_core.h60 u32 reg_data; in reg_set_silent() local
62 reg_data = readl(addr); in reg_set_silent()
63 reg_data &= ~mask; in reg_set_silent()
64 reg_data |= data; in reg_set_silent()
65 writel(reg_data, addr); in reg_set_silent()
79 u16 reg_data; in reg_set_silent16() local
81 reg_data = readw(addr); in reg_set_silent16()
82 reg_data &= ~mask; in reg_set_silent16()
83 reg_data |= data; in reg_set_silent16()
84 writew(reg_data, addr); in reg_set_silent16()
/drivers/ddr/marvell/a38x/old/
A Dddr3_a38x_mc_static.h15 static struct reg_data ddr3_customer_800[] = {
52 struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = {
87 static struct reg_data ddr3_a38x_800[] = {
122 static struct reg_data ddr3_a38x_667[] = {
172 static struct reg_data ddr3_a38x_533[] = {
A Dddr3_training_ip_engine.c187 reg_data, pup_id; in ddr3_tip_ip_training() local
260 reg_data |= 0xe << 14; in ddr3_tip_ip_training()
262 reg_data |= pup_num << 14; in ddr3_tip_ip_training()
266 reg_data |= (0 << 20); in ddr3_tip_ip_training()
268 reg_data |= (0 << 20); in ddr3_tip_ip_training()
270 reg_data |= (3 << 20); in ddr3_tip_ip_training()
298 reg_data = 0x5f + in ddr3_tip_ip_training()
302 reg_data = 0x1f + in ddr3_tip_ip_training()
327 reg_data |= (0x6 << 28); in ddr3_tip_ip_training()
800 u32 reg_data, if_id; in ddr3_tip_load_pattern_to_mem() local
[all …]
A Dddr3_debug.c504 u32 reg_data; in ddr3_tip_print_stability_log() local
562 csindex, &reg_data); in ddr3_tip_print_stability_log()
572 (reg_data & 0x1f) + in ddr3_tip_print_stability_log()
574 (reg_data & 0x1f), in ddr3_tip_print_stability_log()
590 &reg_data); in ddr3_tip_print_stability_log()
592 (reg_data & 0x1f) + in ddr3_tip_print_stability_log()
595 (reg_data & 0x1f), in ddr3_tip_print_stability_log()
616 &reg_data); in ddr3_tip_print_stability_log()
628 idx, &reg_data); in ddr3_tip_print_stability_log()
638 idx, &reg_data); in ddr3_tip_print_stability_log()
[all …]
A Dddr3_training_leveling.c1067 reg_data)); in ddr3_tip_dynamic_write_leveling()
1076 if (reg_data != 0) { in ddr3_tip_dynamic_write_leveling()
1080 if_id, reg_data)); in ddr3_tip_dynamic_write_leveling()
1096 reg_data)); in ddr3_tip_dynamic_write_leveling()
1105 if (reg_data != 0) { in ddr3_tip_dynamic_write_leveling()
1109 if_id, reg_data)); in ddr3_tip_dynamic_write_leveling()
1132 if (reg_data == 0) { in ddr3_tip_dynamic_write_leveling()
1205 reg_data = in ddr3_tip_dynamic_write_leveling()
1213 reg_data = in ddr3_tip_dynamic_write_leveling()
1214 (reg_data & 0x1f) | in ddr3_tip_dynamic_write_leveling()
[all …]
A Dddr3_training_ip_def.h167 struct reg_data { struct
169 u32 reg_data; member
A Dddr3_hws_hw_training.h13 u32 reg_data; member
A Dddr3_training_ip_static.h28 struct reg_data *reg_config_arr);
A Dddr3_training_static.c34 static reg_data *static_init_controller_config[HWS_MAX_DEVICE_NUM];
67 int ddr3_tip_init_specific_reg_config(u32 dev_num, reg_data *reg_config_arr) in ddr3_tip_init_specific_reg_config()
412 reg_data, in ddr3_tip_static_init_controller()
A Dddr3_training_hw_algo.c121 u32 reg_data; in get_valid_win_rx() local
134 &reg_data)); in get_valid_win_rx()
135 res[i] = (reg_data >> RESULT_DB_PHY_REG_RX_OFFSET) & 0x1f; in get_valid_win_rx()
/drivers/net/pfe_eth/
A Dpfe_mdio.c25 u32 reg_data; in pfe_write_addr() local
31 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
33 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
59 u32 reg_data; in pfe_phy_read() local
75 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | in pfe_phy_read()
78 reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA | in pfe_phy_read()
81 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
114 u32 reg_data; in pfe_phy_write() local
129 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | in pfe_phy_write()
132 reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA | in pfe_phy_write()
[all …]
/drivers/spi/
A Dca_sflash.c262 u32 reg_data; in _ca_sflash_read() local
270 *buf++ = reg_data & 0xFF; in _ca_sflash_read()
271 *buf++ = (reg_data >> 8) & 0xFF; in _ca_sflash_read()
276 __func__, reg_data); in _ca_sflash_read()
284 __func__, reg_data); in _ca_sflash_read()
289 *buf++ = reg_data & 0xFF; in _ca_sflash_read()
294 *buf++ = reg_data & 0xFF; in _ca_sflash_read()
298 *buf++ = reg_data & 0xFF; in _ca_sflash_read()
337 u32 reg_data; in _ca_sflash_write() local
342 reg_data = buf[0] in _ca_sflash_write()
[all …]
/drivers/gpio/
A Dbcm6345_gpio.c18 void __iomem *reg_data; member
25 return !!(readl(priv->reg_data) & BIT(offset)); in bcm6345_gpio_get_value()
34 setbits_32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
36 clrbits_32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
96 priv->reg_data = dev_remap_addr_index(dev, 1); in bcm6345_gpio_probe()
97 if (!priv->reg_data) in bcm6345_gpio_probe()
/drivers/ddr/marvell/a38x/
A Dddr3_debug.c589 u32 reg_data; in ddr3_tip_print_stability_log() local
668 reg_data); in ddr3_tip_print_stability_log()
684 reg_data); in ddr3_tip_print_stability_log()
699 &reg_data); in ddr3_tip_print_stability_log()
719 &reg_data); in ddr3_tip_print_stability_log()
732 &reg_data); in ddr3_tip_print_stability_log()
738 &reg_data); in ddr3_tip_print_stability_log()
745 &reg_data); in ddr3_tip_print_stability_log()
757 idx, &reg_data); in ddr3_tip_print_stability_log()
768 idx, &reg_data); in ddr3_tip_print_stability_log()
[all …]
A Dddr3_training_ip_engine.c486 reg_data, pup_id; in ddr3_tip_ip_training() local
560 reg_data |= 0xe << 14; in ddr3_tip_ip_training()
562 reg_data |= pup_num << 14; in ddr3_tip_ip_training()
566 reg_data |= (0 << 20); in ddr3_tip_ip_training()
568 reg_data |= (0 << 20); in ddr3_tip_ip_training()
570 reg_data |= (3 << 20); in ddr3_tip_ip_training()
612 reg_data = CTX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
625 reg_data |= (0x6 << 28); in ddr3_tip_ip_training()
628 reg_data | (init_value << 8), in ddr3_tip_ip_training()
1024 u32 reg_data, if_id; in ddr3_tip_load_pattern_to_mem() local
[all …]
A Dddr3_training_leveling.c917 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
919 reg_data = 0; in ddr3_tip_dynamic_write_leveling()
920 if (reg_data != PASS) in ddr3_tip_dynamic_write_leveling()
930 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
962 reg_data = (reg_data & 0x1f) | in ddr3_tip_dynamic_write_leveling()
1052 reg_data = in ddr3_tip_dynamic_write_leveling()
1060 reg_data = in ddr3_tip_dynamic_write_leveling()
1061 (reg_data & 0x1f) | in ddr3_tip_dynamic_write_leveling()
1063 (((reg_data & 0x1f) + in ddr3_tip_dynamic_write_leveling()
1085 reg_data); in ddr3_tip_dynamic_write_leveling()
[all …]
A Dddr3_training_ip_def.h155 struct reg_data { struct
157 unsigned int reg_data; argument
A Dddr3_training_hw_algo.c116 u32 reg_data; in get_valid_win_rx() local
129 &reg_data)); in get_valid_win_rx()
130 res[i] = (reg_data >> RESULT_PHY_RX_OFFS) & 0x1f; in get_valid_win_rx()
/drivers/pinctrl/
A Dpinctrl-sx150x.c86 u8 reg_data; member
135 .reg_data = 0x00,
155 .reg_data = 0x00,
178 .reg_data = 0x00,
201 .reg_data = 0x00,
220 .reg_data = 0x00,
242 .reg_data = 0x00,
265 .reg_data = 0x08,
286 .reg_data = 0x08,
307 .reg_data = 0x10,
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/drivers/net/
A De1000.c1352 uint32_t reg_data = 0; in e1000_read_mac_addr_from_regs() local
1364 reg_data >>= 16; in e1000_read_mac_addr_from_regs()
1367 tmp = reg_data & 0xffff; in e1000_read_mac_addr_from_regs()
1857 uint32_t reg_data; in e1000_init_hw() local
2002 reg_data &= ~0x00100000; in e1000_init_hw()
2864 uint32_t reg_data; in e1000_copper_link_ggp_setup() local
3221 uint16_t reg_data; in e1000_setup_copper_link() local
3239 reg_data |= 0x3F; in e1000_setup_copper_link()
3255 reg_data = in e1000_setup_copper_link()
4027 uint16_t reg_data; in e1000_configure_kmrn_for_10_100() local
[all …]
A Dks8851_mll.c117 u16 reg_data = 0; in ks_read_config() local
120 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF; in ks_read_config()
121 reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8; in ks_read_config()
124 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; in ks_read_config()
130 if (reg_data & CCR_8BIT) { in ks_read_config()
133 } else if (reg_data & CCR_16BIT) { in ks_read_config()
A Dmvgbe.c191 u32 reg_data; in stop_queue() local
193 reg_data = readl(qreg); in stop_queue()
195 if (reg_data & 0xFF) { in stop_queue()
197 writel((reg_data << 8), qreg); in stop_queue()
205 reg_data = readl(qreg); in stop_queue()
207 while (reg_data & 0xFF); in stop_queue()
/drivers/sound/
A Dwm8994.c292 unsigned short reg_data; in wm8994_hw_params() local
383 if (wm8994_i2c_read(priv, aif1_reg, &reg_data) != 0) { in wm8994_hw_params()
388 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) in wm8994_hw_params()
652 unsigned short reg_data; in wm8994_device_init() local
657 ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, &reg_data); in wm8994_device_init()
663 if (reg_data == WM8994_ID) { in wm8994_device_init()
672 ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, &reg_data); in wm8994_device_init()
677 priv->revision = reg_data; in wm8994_device_init()
/drivers/net/phy/
A Dcortina.c134 char reg_data[0x50] = {0}; in cs4340_upload_firmware() local
275 memcpy(reg_data, &line_temp[i], column_cnt - i); in cs4340_upload_firmware()
277 strim(reg_data); in cs4340_upload_firmware()
279 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
/drivers/power/pmic/
A Drk8xx.c92 static struct reg_data rk806_init_reg[] = {
97 static struct reg_data rk817_init_reg[] = {
252 struct reg_data *init_data = NULL; in rk8xx_probe()

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