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Searched refs:reg_off (Results 1 – 11 of 11) sorted by relevance

/drivers/clk/meson/
A Dg12a.c270 regmap_read(priv->map, parm->reg_off, &reg); in meson_div_get_rate()
364 regmap_update_bits(priv->map, parm->reg_off, in meson_div_set_rate()
477 regmap_read(priv->map, parm->reg_off, &reg); in meson_mux_get_parent()
549 regmap_update_bits(priv->map, parm->reg_off, in meson_mux_set_parent()
668 regmap_read(priv->map, pn2->reg_off, &reg); in meson_mpll_get_rate()
717 regmap_read(priv->map, pn->reg_off, &reg); in meson_pll_get_rate()
720 regmap_read(priv->map, pm->reg_off, &reg); in meson_pll_get_rate()
723 regmap_read(priv->map, pod->reg_off, &reg); in meson_pll_get_rate()
764 regmap_read(priv->map, pn->reg_off, &reg); in meson_pcie_pll_get_rate()
767 regmap_read(priv->map, pm->reg_off, &reg); in meson_pcie_pll_get_rate()
[all …]
A Daxg.c181 regmap_read(priv->map, psdm->reg_off, &reg); in meson_mpll_get_rate()
184 regmap_read(priv->map, pn2->reg_off, &reg); in meson_mpll_get_rate()
225 regmap_read(priv->map, pn->reg_off, &reg); in meson_pll_get_rate()
228 regmap_read(priv->map, pm->reg_off, &reg); in meson_pll_get_rate()
231 regmap_read(priv->map, pod->reg_off, &reg); in meson_pll_get_rate()
A Dgxbb.c312 regmap_read(priv->map, parm->reg_off, &reg); in meson_div_get_rate()
406 regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift), in meson_div_set_rate()
514 regmap_read(priv->map, parm->reg_off, &reg); in meson_mux_get_parent()
586 regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift), in meson_mux_set_parent()
705 regmap_read(priv->map, psdm->reg_off, &reg); in meson_mpll_get_rate()
708 regmap_read(priv->map, pn2->reg_off, &reg); in meson_mpll_get_rate()
749 regmap_read(priv->map, pn->reg_off, &reg); in meson_pll_get_rate()
752 regmap_read(priv->map, pm->reg_off, &reg); in meson_pll_get_rate()
755 regmap_read(priv->map, pod->reg_off, &reg); in meson_pll_get_rate()
A Da1.c38 regmap_update_bits((_priv)->map, (_parm)->reg_off, \
45 regmap_read((_priv)->map, (_parm)->reg_off, &_reg); \
109 .reg_off = (_reg), \
122 .reg_off = (_reg), \
152 .reg_off = (_reg), \
A Dclk_meson.h28 u16 reg_off; member
/drivers/clk/stm32/
A Dclk-stm32-core.h24 u32 reg_off; member
40 u32 reg_off; member
55 u32 reg_off; member
A Dclk-stm32-core.c147 void __iomem *addr = base + gate_cfg->reg_off; in clk_stm32_gate_set_state()
263 mux->reg = priv->base + mux_cfg->reg_off; in clk_stm32_register_composite()
289 div->reg = priv->base + div_cfg->reg_off; in clk_stm32_register_composite()
A Dclk-stm32mp25.c108 .reg_off = (_offset),\
255 .reg_off = (_offset),\
A Dclk-stm32mp13.c153 .reg_off = (_offset), \
320 .reg_off = (_offset), \
451 .reg_off = _offset, \
1684 u32 address = (u32)(priv->base) + stm32mp13_muxes[mux].reg_off; in pkcs_config()
/drivers/net/
A Dcortina_ni.c116 mdio_oper.reg_off = offset; in ca_mdio_write()
180 mdio_oper.reg_off = offset; in ca_mdio_read()
410 u32 reg_off, value; in ca_internal_gphy_cal() local
415 reg_off = priv->gphy_values[i].reg_off + (port * 0x80); in ca_internal_gphy_cal()
417 ca_reg_write(&value, reg_off, 0); in ca_internal_gphy_cal()
1070 &priv->gphy_values[i].reg_off); in ca_ni_of_to_plat()
A Dcortina_ni.h42 u32 reg_off; member
102 u32 reg_off : 5; /* bits 6:2 */ member

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