Searched refs:reg_shift (Results 1 – 13 of 13) sorted by relevance
| /drivers/i2c/ |
| A D | mxc_i2c.c | 165 writeb(idx, base + (IFDR << reg_shift)); in bus_i2c_set_bus_speed()
169 writeb(0, base + (I2SR << reg_shift)); in bus_i2c_set_bus_speed()
186 sr = readb(base + (I2SR << reg_shift)); in wait_for_sr_state()
190 (I2SR << reg_shift)); in wait_for_sr_state()
193 (I2SR << reg_shift)); in wait_for_sr_state()
219 writeb(byte, base + (I2DR << reg_shift)); in tx_byte()
250 writeb(temp, base + (I2CR << reg_shift)); in i2c_imx_stop()
292 temp = readb(base + (I2CR << reg_shift)); in i2c_init_transfer_()
294 writeb(temp, base + (I2CR << reg_shift)); in i2c_init_transfer_()
477 writeb(0, base + (I2SR << reg_shift)); in i2c_early_init_f()
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| A D | ocores_i2c.c | 64 u32 reg_shift; member
88 writeb(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
93 writew(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
98 writel(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
103 out_be16(i2c->base + (reg << i2c->reg_shift), value); in oc_setreg_16be()
113 return readb(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
118 return readw(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16()
123 return readl(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_32()
128 return in_be16(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16be()
133 return in_be32(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_32be()
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| /drivers/net/ |
| A D | dwmac_socfpga.c | 24 u32 reg_shift; member
61 pdata->reg_shift = args.args[1]; in dwmac_socfpga_of_to_plat()
69 u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; in dwmac_socfpga_do_setphy()
79 modereg << pdata->reg_shift); in dwmac_socfpga_do_setphy()
86 modereg << pdata->reg_shift); in dwmac_socfpga_do_setphy()
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| /drivers/power/regulator/ |
| A D | npcm8xx_regulator.c | 22 u32 reg_shift; /* Register bit offset for setting voltage */ member
80 val &= ~BIT(supp->reg_shift); in npcm8xx_regulator_set_value()
81 val |= level << supp->reg_shift; in npcm8xx_regulator_set_value()
101 val = readl(REG_VSRCR) & BIT(supp->reg_shift); in npcm8xx_regulator_get_value()
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| /drivers/serial/ |
| A D | ns16550.c | 122 writeb(value, addr + (1 << plat->reg_shift) - 1); in serial_out_dynamic()
142 return readb(addr + (1 << plat->reg_shift) - 1); in serial_in_dynamic()
165 offset *= 1 << plat->reg_shift; in ns16550_writeb()
171 serial_out_shift(addr, plat->reg_shift, value); in ns16550_writeb()
179 offset *= 1 << plat->reg_shift; in ns16550_readb()
185 return serial_in_shift(addr, plat->reg_shift); in ns16550_readb()
475 info->reg_shift = plat->reg_shift; in ns16550_serial_getinfo()
552 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); in ns16550_serial_of_to_plat()
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| A D | serial_rockchip.c | 32 plat->plat.reg_shift = plat->dtplat.reg_shift; in rockchip_serial_probe()
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| A D | serial_coreboot.c | 86 plat->reg_shift = addr->access_size - 1; in read_dbg2()
104 plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0; in coreboot_of_to_plat()
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| A D | serial_intel_mid.c | 27 offset *= 1 << plat->reg_shift; in mid_writel()
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| A D | serial_omap.c | 123 plat->reg_shift = 2; in omap_serial_of_to_plat()
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| A D | sandbox.c | 213 .reg_shift = 0, in sandbox_serial_getinfo()
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| A D | serial_pl01x.c | 291 info->reg_shift = 2; in pl01x_serial_getinfo()
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| /drivers/gpio/ |
| A D | hsdk-creg-gpio.c | 33 u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_set_value() local
36 reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift); in hsdk_creg_gpio_set_value()
37 reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift); in hsdk_creg_gpio_set_value()
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| /drivers/video/exynos/ |
| A D | exynos_dp_lowlevel.c | 922 unsigned int reg_shift[DP_LANE_CNT_4] = { in exynos_dp_set_lane_pre_emphasis() local
930 reg = level << reg_shift[i]; in exynos_dp_set_lane_pre_emphasis()
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