Searched refs:reg_value (Results 1 – 10 of 10) sorted by relevance
| /drivers/ram/k3-ddrss/ |
| A D | cps_drv_lpddr4.h | 30 (u32)(reg_value)))
34 (u32)(reg_value), (u32)(value)))
36 #define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \ argument
39 (u32)(reg_value)))
46 (u32)(reg_value)))
61 static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
62 static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value) in cps_fldread() argument
64 u32 result = (reg_value & mask) >> shift; in cps_fldread()
74 new_value = (reg_value & ~mask) | new_value; in cps_fldwrite()
81 u32 new_value = reg_value; in cps_fldset()
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| /drivers/ram/rockchip/ |
| A D | sdram_rk3399.c | 356 u32 reg_value; in phy_io_config() local
584 u32 reg_value; in set_ds_odt() local
1909 u32 reg_value; in set_lpddr4_dq_odt() local
1915 reg_value = 0; in set_lpddr4_dq_odt()
1956 u32 reg_value; in set_lpddr4_ca_odt() local
1962 reg_value = 0; in set_lpddr4_ca_odt()
2003 u32 reg_value; in set_lpddr4_MR3() local
2021 reg_value << 16); in set_lpddr4_MR3()
2023 reg_value << 16); in set_lpddr4_MR3()
2050 u32 reg_value; in set_lpddr4_MR12() local
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| /drivers/net/phy/ |
| A D | cortina.c | 279 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
281 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
291 int reg_value; in cs4340_phy_init() local
305 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
306 if (reg_value & mseq_edc_bist_done) { in cs4340_phy_init()
307 if (0 == (reg_value & mseq_edc_bist_fail)) in cs4340_phy_init()
321 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
322 if (reg_value) { in cs4340_phy_init()
354 int reg_value; in cs4223_phy_init() local
356 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); in cs4223_phy_init()
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| /drivers/led/ |
| A D | led_cortina.c | 172 u32 reg_value, val; in cortina_led_probe() local
178 reg_value = 0; in cortina_led_probe()
179 reg_value |= LED_CLK_POLARITY; in cortina_led_probe()
187 reg_value |= (rate1 & LED_BLINK_RATE1_MASK) << in cortina_led_probe()
193 reg_value |= (rate2 & LED_BLINK_RATE2_MASK) << in cortina_led_probe()
196 cortina_led_write(plat->ctrl_regs, reg_value); in cortina_led_probe()
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| /drivers/video/sunxi/ |
| A D | sunxi_de2.c | 39 u32 reg_value; in sunxi_de2_composer_init() local
42 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
43 reg_value &= ~(0x01 << 24); in sunxi_de2_composer_init()
44 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
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| /drivers/usb/musb-new/ |
| A D | sunxi.c | 175 u32 reg_value; in USBC_ConfigFIFO_Base() local
178 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
179 reg_value &= ~(0x03 << 0); in USBC_ConfigFIFO_Base()
180 reg_value |= BIT(0); in USBC_ConfigFIFO_Base()
181 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
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| /drivers/phy/allwinner/ |
| A D | phy-sun4i-usb.c | 157 u32 bits, reg_value; in sun4i_usb_phy_passby() local
170 reg_value = readl(usb_phy->pmu); in sun4i_usb_phy_passby()
173 reg_value |= bits; in sun4i_usb_phy_passby()
175 reg_value &= ~bits; in sun4i_usb_phy_passby()
177 writel(reg_value, usb_phy->pmu); in sun4i_usb_phy_passby()
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| /drivers/ddr/marvell/axp/ |
| A D | ddr3_hw_training.h | 288 u32 reg_value; member
293 u32 reg_value; member
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| A D | ddr3_init.c | 795 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
893 ddr_mode->regs[j].reg_value); in ddr3_static_mc_init()
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| /drivers/net/ |
| A D | cortina_ni.c | 964 int ret, reg_value; in cortina_eth_probe() local
993 ca_reg_read(®_value, (u64)priv->per_mdio_base_addr, in cortina_eth_probe()
995 reg_value = reg_value | 0x00280000; in cortina_eth_probe()
996 ca_reg_write(®_value, (u64)priv->per_mdio_base_addr, in cortina_eth_probe()
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