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Searched refs:reg_write (Results 1 – 23 of 23) sorted by relevance

/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c79 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw()
502 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw_reg_dimm()
673 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_sw()
687 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw()
807 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw()
845 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw()
897 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_sw_reg_dimm()
922 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm()
995 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm()
1039 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_init.c166 reg_write(0x8c04, 0x40000000); in ddr3_restore_and_set_final_windows()
206 reg_write(0x8c04, 0); in ddr3_save_and_set_training_windows()
223 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
258 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
478 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
535 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0); in ddr3_init_main()
563 reg_write(DLB_EVICTION_CONTROL_REG, 0x0); in ddr3_init_main()
648 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
658 reg_write(REG_BOOTROM_ROUTINE_ADDR, in ddr3_init_main()
794 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
[all …]
A Dxor.c41 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
45 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
47 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
71 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
74 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init()
88 reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup); in mv_sys_xor_finish()
90 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish()
92 reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]); in mv_sys_xor_finish()
94 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
186 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
[all …]
A Dddr3_spd.c787 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
963 reg_write(REG_DDR_CONT_HIGH_ADDR, reg);
970 reg_write(0x142C, reg);
1075 reg_write(REG_DDR3_MR0_CS_ADDR +
1088 reg_write(REG_DDR3_MR1_CS_ADDR +
1126 reg_write(REG_DDR3_MR2_CS_ADDR +
1135 reg_write(REG_DDR3_MR3_CS_ADDR +
1147 reg_write(REG_ODT_TIME_LOW_ADDR, reg);
1153 reg_write(REG_ODT_TIME_HIGH_ADDR, reg);
1182 reg_write(REG_ZQC_CONF_ADDR, reg);
[all …]
A Dddr3_hw_training.c110 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
542 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg); in ddr3_set_performance_params()
630 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
647 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
651 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_load_patterns()
655 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0); in ddr3_load_patterns()
660 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, in ddr3_load_patterns()
675 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_load_patterns()
936 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_training_suspend_resume()
1081 reg_write(REG_DUNIT_ODT_CTRL_ADDR, reg); in ddr3_odt_activate()
[all …]
A Dddr3_read_leveling.c80 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_read_leveling_hw()
193 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
211 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
301 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
311 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
324 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
448 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_single_cs_rl_mode()
623 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, in ddr3_read_leveling_single_cs_rl_mode()
726 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_single_cs_rl_mode()
802 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_single_cs_window_mode()
[all …]
A Dddr3_pbs.c112 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
163 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
287 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
384 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
388 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_pbs_tx()
555 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
605 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
677 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
695 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
896 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
[all …]
A Dddr3_dqs.c143 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
147 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx()
162 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
189 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
196 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
200 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_dqs_centralization_rx()
225 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
242 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
269 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
276 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
[all …]
A Dddr3_sdram.c69 reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)), in xor_waiton_eng()
510 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
517 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
645 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
653 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_reset_phy_read_fifo()
666 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
A Dddr3_init.h121 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/drivers/ddr/marvell/a38x/
A Dxor.c46 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
81 reg_write(XOR_BASE_ADDR_REG(0, ui), (u32)base); in mv_sys_xor_init()
85 reg_write(XOR_SIZE_MASK_REG(0, ui), (u32)size_mask); in mv_sys_xor_init()
98 reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup); in mv_sys_xor_finish()
100 reg_write(XOR_BASE_ADDR_REG(0, ui), in mv_sys_xor_finish()
103 reg_write(XOR_SIZE_MASK_REG(0, ui), in mv_sys_xor_finish()
106 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
200 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
207 reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low); in mv_xor_mem_init()
[all …]
A Dmv_ddr_plat.c281 reg_write(TSEN_CONTROL_LSB_REG, reg); in ddr3_ctrl_get_junc_temp()
336 reg_write(addr, reg_val); in dunit_write()
455 reg_write(DUAL_DUNIT_CFG_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
1283 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
1319 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
1383 reg_write(TRAINING_DBG_3_REG, reg_val); in mv_ddr_pre_training_soc_config()
1391 reg_write(AXI_CTRL_REG, 0); in mv_ddr_pre_training_soc_config()
1409 reg_write(config_table_ptr[i].reg_addr, in ddr3_new_tip_dlb_config()
1418 reg_write(DUNIT_CTRL_HIGH_REG, reg); in ddr3_new_tip_dlb_config()
1435 reg_write(DLB_CTRL_REG, reg); in ddr3_new_tip_dlb_config()
[all …]
A Dmv_ddr_sys_env_lib.c71 reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg); in mv_ddr_sys_env_suspend_wakeup_check()
76 reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg); in mv_ddr_sys_env_suspend_wakeup_check()
A Dddr_ml_wrapper.h124 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/drivers/ddr/marvell/a38x/old/
A Dddr3_init.c188 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); in ddr3_restore_and_set_final_windows()
206 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg); in ddr3_restore_and_set_final_windows()
228 reg_write(ADDRESS_FILTERING_END_REGISTER, 0); in ddr3_save_and_set_training_windows()
235 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
271 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
353 reg_write(REG_TRAINING_DEBUG_3_ADDR, reg); in ddr3_init()
361 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0); in ddr3_init()
406 reg_write(REG_BOOTROM_ROUTINE_ADDR, in ddr3_init()
567 reg_write(config_table_ptr[i].reg_addr, in ddr3_new_tip_dlb_config()
576 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg); in ddr3_new_tip_dlb_config()
[all …]
A Dddr3_a38x.c298 reg_write(reg_addr, data_value); in ddr3_tip_a38x_if_write()
337 reg_write(CS_ENABLE_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
A Dddr3_init.h385 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/drivers/spi/
A Dmxc_spi.c103 #define reg_write(a, v) writel(v, a) macro
238 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
240 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
294 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
296 reg_write(&regs->cfg, reg_config); in spi_cfg_mxc()
303 reg_write(&regs->intr, 0); in spi_cfg_mxc()
328 reg_write(&regs->cfg, mxcs->cfg_reg); in spi_xchg_single()
349 reg_write(&regs->txdata, data); in spi_xchg_single()
370 reg_write(&regs->txdata, data); in spi_xchg_single()
471 reg_write(&regs->rxdata, 1); in mxc_spi_claim_bus_internal()
[all …]
/drivers/net/mtk_eth/
A Dmt753x.c81 return priv->reg_write(priv, reg, data); in mt753x_reg_write()
91 priv->reg_write(priv, reg, val); in mt753x_reg_rmw()
A Dmt7988.c71 priv->reg_write = mt7988_reg_write; in mt7988_setup()
A Dmt753x.h263 int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data); member
A Dmt7530.c156 priv->reg_write = mt753x_mdio_reg_write; in mt7530_setup()
A Dmt7531.c179 priv->reg_write = mt753x_mdio_reg_write; in mt7531_setup()

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