| /drivers/video/nexell/soc/ |
| A D | s5pxx18_soc_mipi.c | 68 register u32 regvalue; in nx_mipi_set_interrupt_enable() local
97 register u32 regvalue; in nx_mipi_get_interrupt_pending() local
156 if (regvalue) in nx_mipi_get_interrupt_pending_all()
162 if (regvalue) in nx_mipi_get_interrupt_pending_all()
185 if (regvalue != 0) { in nx_mipi_get_interrupt_pending_number()
189 regvalue >>= 1; in nx_mipi_get_interrupt_pending_number()
195 if (regvalue != 0) { in nx_mipi_get_interrupt_pending_number()
199 regvalue >>= 1; in nx_mipi_get_interrupt_pending_number()
207 regvalue = (regvalue & (~(mask))) | (value); \
287 regvalue = 0; in nx_mipi_dsi_set_clock()
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| A D | s5pxx18_soc_disptop.c | 61 u32 regvalue; in nx_disp_top_set_resconvmux() local
71 u32 regvalue; in nx_disp_top_set_hdmimux() local
81 u32 regvalue; in nx_disp_top_set_mipimux() local
163 regvalue = regvalue & (~(0x7 << 3)); in nx_disp_top_set_padclock()
164 regvalue = regvalue | (padclk_cfg << 3); in nx_disp_top_set_padclock()
166 regvalue = regvalue & (~(0x7 << 6)); in nx_disp_top_set_padclock()
167 regvalue = regvalue | (padclk_cfg << 6); in nx_disp_top_set_padclock()
169 regvalue = regvalue & (~(0x7 << 0)); in nx_disp_top_set_padclock()
170 regvalue = regvalue | (padclk_cfg << 0); in nx_disp_top_set_padclock()
182 regvalue = regvalue & (~(0x1 << 9)); in nx_disp_top_set_lcdif_enb()
[all …]
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| A D | s5pxx18_soc_lvds.c | 88 writel(regvalue, &pregister->lvdsctrl0); in nx_lvds_set_lvdsctrl0()
96 writel(regvalue, &pregister->lvdsctrl1); in nx_lvds_set_lvdsctrl1()
104 writel(regvalue, &pregister->lvdsctrl2); in nx_lvds_set_lvdsctrl2()
112 writel(regvalue, &pregister->lvdsctrl3); in nx_lvds_set_lvdsctrl3()
120 writel(regvalue, &pregister->lvdsctrl4); in nx_lvds_set_lvdsctrl4()
136 writel(regvalue, &pregister->lvdsloc0); in nx_lvds_set_lvdsloc0()
144 writel(regvalue, &pregister->lvdsloc1); in nx_lvds_set_lvdsloc1()
152 writel(regvalue, &pregister->lvdsloc2); in nx_lvds_set_lvdsloc2()
160 writel(regvalue, &pregister->lvdsloc3); in nx_lvds_set_lvdsloc3()
168 writel(regvalue, &pregister->lvdsloc4); in nx_lvds_set_lvdsloc4()
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| A D | s5pxx18_soc_lvds.h | 54 void nx_lvds_set_lvdsctrl0(u32 module_index, u32 regvalue);
55 void nx_lvds_set_lvdsctrl1(u32 module_index, u32 regvalue);
56 void nx_lvds_set_lvdsctrl2(u32 module_index, u32 regvalue);
57 void nx_lvds_set_lvdsctrl3(u32 module_index, u32 regvalue);
58 void nx_lvds_set_lvdsctrl4(u32 module_index, u32 regvalue);
66 void nx_lvds_set_lvdsloc0(u32 module_index, u32 regvalue);
67 void nx_lvds_set_lvdsloc1(u32 module_index, u32 regvalue);
68 void nx_lvds_set_lvdsloc2(u32 module_index, u32 regvalue);
69 void nx_lvds_set_lvdsloc3(u32 module_index, u32 regvalue);
70 void nx_lvds_set_lvdsloc4(u32 module_index, u32 regvalue);
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| A D | s5pxx18_soc_mlc.c | 53 register u32 regvalue; in nx_mlc_set_clock_pclk_mode() local
106 regvalue &= ~(0x3); in nx_mlc_set_clock_bclk_mode()
1302 u32 regvalue; in nx_mlc_set_gamma_table_poweroff() local
1307 regvalue = regvalue & 0xf3; in nx_mlc_set_gamma_table_poweroff()
1343 u32 regvalue; in nx_mlc_set_rgb0layer_control_parameter() local
1354 regvalue = in nx_mlc_set_rgb0layer_control_parameter()
1392 u32 regvalue; in nx_mlc_set_rgb1layer_control_parameter() local
1403 regvalue = in nx_mlc_set_rgb1layer_control_parameter()
1426 u32 regvalue; in nx_mlc_set_rgb2layer_control_parameter() local
1437 regvalue = in nx_mlc_set_rgb2layer_control_parameter()
[all …]
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| A D | s5pxx18_soc_hdmi.c | 18 u32 regvalue; in nx_hdmi_get_reg() local
21 regvalue = readl((u32 *)reg_addr); in nx_hdmi_get_reg()
23 return regvalue; in nx_hdmi_get_reg()
26 void nx_hdmi_set_reg(u32 module_index, u32 offset, u32 regvalue) in nx_hdmi_set_reg() argument
32 writel(regvalue, (u32 *)reg_addr); in nx_hdmi_set_reg()
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| A D | s5pxx18_soc_dpc.c | 60 register u32 regvalue; in nx_dpc_set_interrupt_enable() local
128 register u32 regvalue; in nx_dpc_clear_interrupt_pending() local
157 register u32 regvalue; in nx_dpc_set_interrupt_enable_all() local
919 regvalue = 0; in nx_dpc_set_horizontal_up_scaler()
961 u32 regvalue = 0; in nx_dpc_set_sync() local
1005 u32 regvalue; in nx_dpc_set_output_format() local
1023 u32 regvalue; in nx_dpc_set_quantization_mode() local
1034 u32 regvalue; in nx_dpc_set_enable() local
1115 u32 regvalue; in nx_dpc_set_index() local
1217 u32 regvalue; in nx_dpc_get_field_flag() local
[all …]
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| A D | s5pxx18_soc_disptop_clk.c | 66 register u32 regvalue; in nx_disp_top_clkgen_set_clock_bclk_mode() local
83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
84 regvalue &= ~3ul; in nx_disp_top_clkgen_set_clock_bclk_mode()
85 regvalue |= (clkmode & 0x03); in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
115 register u32 regvalue; in nx_disp_top_clkgen_set_clock_pclk_mode() local
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
132 regvalue &= ~(1ul << pclkmode_pos); in nx_disp_top_clkgen_set_clock_pclk_mode()
133 regvalue |= (clkmode & 0x01) << pclkmode_pos; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
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| A D | s5pxx18_soc_hdmi.h | 482 void nx_hdmi_set_reg(u32 module_index, u32 offset, u32 regvalue);
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| A D | s5pxx18_soc_dpc.h | 369 void nx_dpc_set_pad_location(u32 module_index, u32 index, u32 regvalue);
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| /drivers/ram/k3-ddrss/ |
| A D | lpddr4_obj_if.h | 21 u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
23 u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
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| A D | lpddr4_if.h | 84 u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
86 u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
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| A D | lpddr4_sanity.h | 22 …ddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
130 …pddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue) in lpddr4_sanityfunction4() argument
134 if (regvalue == NULL) { in lpddr4_sanityfunction4()
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| A D | lpddr4.c | 166 u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue) in lpddr4_readreg() argument
170 result = lpddr4_readregsf(pd, cpp, regvalue); in lpddr4_readreg()
178 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset)); in lpddr4_readreg()
183 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset)); in lpddr4_readreg()
189 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset)); in lpddr4_readreg()
260 u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue) in lpddr4_writereg() argument
272 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue); in lpddr4_writereg()
277 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue); in lpddr4_writereg()
282 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue); in lpddr4_writereg()
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