1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH QSPI (Quad SPI) driver
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 */
8
9 #define LOG_CATEGORY UCLASS_SPI
10
11 #include <console.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <wait_bit.h>
15 #include <asm/arch/renesas.h>
16 #include <asm/io.h>
17 #include <linux/bitops.h>
18
19 /* SH QSPI register bit masks <REG>_<BIT> */
20 #define SPCR_MSTR 0x08
21 #define SPCR_SPE 0x40
22 #define SPSR_SPRFF 0x80
23 #define SPSR_SPTEF 0x20
24 #define SPPCR_IO3FV 0x04
25 #define SPPCR_IO2FV 0x02
26 #define SPPCR_IO1FV 0x01
27 #define SPBDCR_RXBC0 BIT(0)
28 #define SPCMD_SCKDEN BIT(15)
29 #define SPCMD_SLNDEN BIT(14)
30 #define SPCMD_SPNDEN BIT(13)
31 #define SPCMD_SSLKP BIT(7)
32 #define SPCMD_BRDV0 BIT(2)
33 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
34 SPCMD_SPNDEN | SPCMD_SSLKP | \
35 SPCMD_BRDV0
36 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
37 SPCMD_BRDV0
38 #define SPBFCR_TXRST BIT(7)
39 #define SPBFCR_RXRST BIT(6)
40 #define SPBFCR_TXTRG 0x30
41 #define SPBFCR_RXTRG 0x07
42
43 /* SH QSPI register set */
44 struct sh_qspi_regs {
45 u8 spcr;
46 u8 sslp;
47 u8 sppcr;
48 u8 spsr;
49 u32 spdr;
50 u8 spscr;
51 u8 spssr;
52 u8 spbr;
53 u8 spdcr;
54 u8 spckd;
55 u8 sslnd;
56 u8 spnd;
57 u8 dummy0;
58 u16 spcmd0;
59 u16 spcmd1;
60 u16 spcmd2;
61 u16 spcmd3;
62 u8 spbfcr;
63 u8 dummy1;
64 u16 spbdcr;
65 u32 spbmul0;
66 u32 spbmul1;
67 u32 spbmul2;
68 u32 spbmul3;
69 };
70
71 struct sh_qspi_slave {
72 #if !CONFIG_IS_ENABLED(DM_SPI)
73 struct spi_slave slave;
74 #endif
75 struct sh_qspi_regs *regs;
76 };
77
sh_qspi_init(struct sh_qspi_slave * ss)78 static void sh_qspi_init(struct sh_qspi_slave *ss)
79 {
80 /* QSPI initialize */
81 /* Set master mode only */
82 writeb(SPCR_MSTR, &ss->regs->spcr);
83
84 /* Set SSL signal level */
85 writeb(0x00, &ss->regs->sslp);
86
87 /* Set MOSI signal value when transfer is in idle state */
88 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
89
90 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
91 writeb(0x01, &ss->regs->spbr);
92
93 /* Disable Dummy Data Transmission */
94 writeb(0x00, &ss->regs->spdcr);
95
96 /* Set clock delay value */
97 writeb(0x00, &ss->regs->spckd);
98
99 /* Set SSL negation delay value */
100 writeb(0x00, &ss->regs->sslnd);
101
102 /* Set next-access delay value */
103 writeb(0x00, &ss->regs->spnd);
104
105 /* Set equence command */
106 writew(SPCMD_INIT2, &ss->regs->spcmd0);
107
108 /* Reset transfer and receive Buffer */
109 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
110
111 /* Clear transfer and receive Buffer control bit */
112 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
113
114 /* Set equence control method. Use equence0 only */
115 writeb(0x00, &ss->regs->spscr);
116
117 /* Enable SPI function */
118 setbits_8(&ss->regs->spcr, SPCR_SPE);
119 }
120
sh_qspi_cs_activate(struct sh_qspi_slave * ss)121 static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
122 {
123 /* Set master mode only */
124 writeb(SPCR_MSTR, &ss->regs->spcr);
125
126 /* Set command */
127 writew(SPCMD_INIT1, &ss->regs->spcmd0);
128
129 /* Reset transfer and receive Buffer */
130 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
131
132 /* Clear transfer and receive Buffer control bit */
133 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
134
135 /* Set equence control method. Use equence0 only */
136 writeb(0x00, &ss->regs->spscr);
137
138 /* Enable SPI function */
139 setbits_8(&ss->regs->spcr, SPCR_SPE);
140 }
141
sh_qspi_cs_deactivate(struct sh_qspi_slave * ss)142 static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
143 {
144 /* Disable SPI Function */
145 clrbits_8(&ss->regs->spcr, SPCR_SPE);
146 }
147
sh_qspi_xfer_common(struct sh_qspi_slave * ss,unsigned int bitlen,const void * dout,void * din,unsigned long flags)148 static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
149 const void *dout, void *din, unsigned long flags)
150 {
151 u32 nbyte, chunk;
152 int i, ret = 0;
153 u8 dtdata = 0, drdata;
154 u8 *tdata = &dtdata, *rdata = &drdata;
155 u32 *spbmul0 = &ss->regs->spbmul0;
156
157 if (dout == NULL && din == NULL) {
158 if (flags & SPI_XFER_END)
159 sh_qspi_cs_deactivate(ss);
160 return 0;
161 }
162
163 if (bitlen % 8) {
164 log_warning("bitlen is not 8bit aligned %d", bitlen);
165 return 1;
166 }
167
168 nbyte = bitlen / 8;
169
170 if (flags & SPI_XFER_BEGIN) {
171 sh_qspi_cs_activate(ss);
172
173 /* Set 1048576 byte */
174 writel(0x100000, spbmul0);
175 }
176
177 if (flags & SPI_XFER_END)
178 writel(nbyte, spbmul0);
179
180 if (dout != NULL)
181 tdata = (u8 *)dout;
182
183 if (din != NULL)
184 rdata = din;
185
186 while (nbyte > 0) {
187 /*
188 * Check if there is 32 Byte chunk and if there is, transfer
189 * it in one burst, otherwise transfer on byte-by-byte basis.
190 */
191 chunk = (nbyte >= 32) ? 32 : 1;
192
193 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
194 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
195
196 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
197 true, 1000, true);
198 if (ret)
199 return ret;
200
201 for (i = 0; i < chunk; i++) {
202 writeb(*tdata, &ss->regs->spdr);
203 if (dout != NULL)
204 tdata++;
205 }
206
207 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
208 true, 1000, true);
209 if (ret)
210 return ret;
211
212 for (i = 0; i < chunk; i++) {
213 *rdata = readb(&ss->regs->spdr);
214 if (din != NULL)
215 rdata++;
216 }
217
218 nbyte -= chunk;
219 }
220
221 if (flags & SPI_XFER_END)
222 sh_qspi_cs_deactivate(ss);
223
224 return ret;
225 }
226
227 #if !CONFIG_IS_ENABLED(DM_SPI)
to_sh_qspi(struct spi_slave * slave)228 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
229 {
230 return container_of(slave, struct sh_qspi_slave, slave);
231 }
232
spi_cs_is_valid(unsigned int bus,unsigned int cs)233 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
234 {
235 return 1;
236 }
237
spi_cs_activate(struct spi_slave * slave)238 void spi_cs_activate(struct spi_slave *slave)
239 {
240 struct sh_qspi_slave *ss = to_sh_qspi(slave);
241
242 sh_qspi_cs_activate(ss);
243 }
244
spi_cs_deactivate(struct spi_slave * slave)245 void spi_cs_deactivate(struct spi_slave *slave)
246 {
247 struct sh_qspi_slave *ss = to_sh_qspi(slave);
248
249 sh_qspi_cs_deactivate(ss);
250 }
251
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)252 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
253 unsigned int max_hz, unsigned int mode)
254 {
255 struct sh_qspi_slave *ss;
256
257 if (!spi_cs_is_valid(bus, cs))
258 return NULL;
259
260 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
261 if (!ss) {
262 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
263 return NULL;
264 }
265
266 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
267
268 /* Init SH QSPI */
269 sh_qspi_init(ss);
270
271 return &ss->slave;
272 }
273
spi_free_slave(struct spi_slave * slave)274 void spi_free_slave(struct spi_slave *slave)
275 {
276 struct sh_qspi_slave *spi = to_sh_qspi(slave);
277
278 free(spi);
279 }
280
spi_claim_bus(struct spi_slave * slave)281 int spi_claim_bus(struct spi_slave *slave)
282 {
283 return 0;
284 }
285
spi_release_bus(struct spi_slave * slave)286 void spi_release_bus(struct spi_slave *slave)
287 {
288 }
289
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)290 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
291 const void *dout, void *din, unsigned long flags)
292 {
293 struct sh_qspi_slave *ss = to_sh_qspi(slave);
294
295 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
296 }
297
298 #else
299
300 #include <dm.h>
301
sh_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)302 static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
303 const void *dout, void *din, unsigned long flags)
304 {
305 struct udevice *bus = dev->parent;
306 struct sh_qspi_slave *ss = dev_get_plat(bus);
307
308 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
309 }
310
sh_qspi_set_speed(struct udevice * dev,uint speed)311 static int sh_qspi_set_speed(struct udevice *dev, uint speed)
312 {
313 /* This is a SPI NOR controller, do nothing. */
314 return 0;
315 }
316
sh_qspi_set_mode(struct udevice * dev,uint mode)317 static int sh_qspi_set_mode(struct udevice *dev, uint mode)
318 {
319 /* This is a SPI NOR controller, do nothing. */
320 return 0;
321 }
322
sh_qspi_probe(struct udevice * dev)323 static int sh_qspi_probe(struct udevice *dev)
324 {
325 struct sh_qspi_slave *ss = dev_get_plat(dev);
326
327 sh_qspi_init(ss);
328
329 return 0;
330 }
331
sh_qspi_of_to_plat(struct udevice * dev)332 static int sh_qspi_of_to_plat(struct udevice *dev)
333 {
334 struct sh_qspi_slave *plat = dev_get_plat(dev);
335
336 plat->regs = dev_read_addr_ptr(dev);
337
338 return 0;
339 }
340
341 static const struct dm_spi_ops sh_qspi_ops = {
342 .xfer = sh_qspi_xfer,
343 .set_speed = sh_qspi_set_speed,
344 .set_mode = sh_qspi_set_mode,
345 };
346
347 static const struct udevice_id sh_qspi_ids[] = {
348 { .compatible = "renesas,qspi" },
349 { }
350 };
351
352 U_BOOT_DRIVER(sh_qspi) = {
353 .name = "sh_qspi",
354 .id = UCLASS_SPI,
355 .of_match = sh_qspi_ids,
356 .ops = &sh_qspi_ops,
357 .of_to_plat = sh_qspi_of_to_plat,
358 .plat_auto = sizeof(struct sh_qspi_slave),
359 .probe = sh_qspi_probe,
360 };
361 #endif
362