Searched refs:timing_info (Results 1 – 2 of 2) sorted by relevance
192 sizeof(*timing_info)); in dram_config_save()196 for (i = 0; i < timing_info->ddrc_cfg_num; i++) { in dram_config_save()197 cfg->reg = timing_info->ddrc_cfg[i].reg; in dram_config_save()198 cfg->val = timing_info->ddrc_cfg[i].val; in dram_config_save()204 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { in dram_config_save()205 cfg->reg = timing_info->ddrphy_cfg[i].reg; in dram_config_save()206 cfg->val = timing_info->ddrphy_cfg[i].val; in dram_config_save()213 cfg->reg = timing_info->ddrphy_trained_csr[i].reg; in dram_config_save()214 cfg->val = timing_info->ddrphy_trained_csr[i].val; in dram_config_save()221 cfg->reg = timing_info->ddrphy_pie[i].reg; in dram_config_save()[all …]
221 saved_timing->ctl_cfg_num = timing_info->ctl_cfg_num; in save_dram_config()230 sizeof(*timing_info)); in save_dram_config()234 for (i = 0; i < timing_info->ctl_cfg_num; i++) { in save_dram_config()235 cfg->reg = timing_info->ctl_cfg[i].reg; in save_dram_config()236 cfg->val = timing_info->ctl_cfg[i].val; in save_dram_config()242 for (i = 0; i < timing_info->phy_f1_cfg_num; i++) { in save_dram_config()243 cfg->reg = timing_info->phy_f1_cfg[i].reg; in save_dram_config()244 cfg->val = timing_info->phy_f1_cfg[i].val; in save_dram_config()250 for (i = 0; i < timing_info->phy_f2_cfg_num; i++) { in save_dram_config()251 cfg->reg = timing_info->phy_f2_cfg[i].reg; in save_dram_config()[all …]
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