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Searched refs:ui (Results 1 – 10 of 10) sorted by relevance

/drivers/phy/
A Dphy-core-mipi-dphy.c24 unsigned long long ui; in phy_mipi_dphy_get_default_config() local
33 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
36 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
46 cfg->hs_prepare = 40000 + 4 * ui; in phy_mipi_dphy_get_default_config()
47 cfg->hs_zero = 105000 + 6 * ui; in phy_mipi_dphy_get_default_config()
48 cfg->hs_settle = 85000 + 6 * ui; in phy_mipi_dphy_get_default_config()
62 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); in phy_mipi_dphy_get_default_config()
83 unsigned long long ui; in phy_mipi_dphy_config_validate() local
89 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
118 if (cfg->eot > (105000 + 12 * ui)) in phy_mipi_dphy_config_validate()
[all …]
/drivers/ddr/marvell/a38x/
A Dxor.c23 u32 reg, ui, cs_count; in mv_sys_xor_init() local
27 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_init()
30 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_init()
35 for (ui = 0, cs_count = 0; in mv_sys_xor_init()
37 ui++, cs_count++) { in mv_sys_xor_init()
40 reg |= (0x1 << (ui)); in mv_sys_xor_init()
51 ui++, cs_count++) { in mv_sys_xor_init()
60 switch (ui) { in mv_sys_xor_init()
96 u32 ui; in mv_sys_xor_finish() local
99 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_finish()
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A Dddr3_debug.c1416 u32 ui, uj; in print_topology() local
1424 for (ui = 0; ui < MAX_INTERFACE_NUM; ui++) { in print_topology()
1425 VALIDATE_IF_ACTIVE(topology_db->if_act_mask, ui); in print_topology()
1426 printf("\n\tInterface ID: %d\n", ui); in print_topology()
1429 interface_params[ui].memory_freq)); in print_topology()
1436 interface_params[ui].memory_size)); in print_topology()
1440 topology_db->interface_params[ui].cas_l); in print_topology()
1446 topology_db->interface_params[ui]. in print_topology()
1449 topology_db->interface_params[ui]. in print_topology()
1453 interface_params[ui].as_bus_params[uj]. in print_topology()
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A Dmv_ddr_plat.c1227 u32 ui; in ddr3_restore_and_set_final_windows() local
1233 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
1234 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); in ddr3_restore_and_set_final_windows()
1261 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
1286 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
1287 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
/drivers/ddr/marvell/axp/
A Dxor.c28 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()
29 xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
30 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()
31 xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
34 for (ui = 0; ui < (dram_info->num_cs + 1); ui++) { in mv_sys_xor_init()
50 for (ui = 0; ui < MAX_CS; ui++) { in mv_sys_xor_init()
56 switch (ui) { in mv_sys_xor_init()
86 u32 ui; in mv_sys_xor_finish() local
89 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
90 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish()
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A Dddr3_sdram.c290 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
335 for (ui = 0; ui < LEN_PBS_PATTERN; ui++) { in ddr3_sdram_pbs_compare()
336 if ((sdram_data[ui]) != (pattern_ptr[ui])) { in ddr3_sdram_pbs_compare()
341 var1 = ((sdram_data[ui] >> val) & in ddr3_sdram_pbs_compare()
343 var2 = ((pattern_ptr[ui] >> val) & in ddr3_sdram_pbs_compare()
349 (ui % pup_groups)); in ddr3_sdram_pbs_compare()
583 u32 ui; in ddr3_dram_sram_read() local
589 for (ui = 0; ui < len; ui++) { in ddr3_dram_sram_read()
A Dddr3_init.c141 u32 ui, reg, cs; in ddr3_restore_and_set_final_windows() local
159 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
160 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]); in ddr3_restore_and_set_final_windows()
200 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
226 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
227 win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
/drivers/ddr/marvell/a38x/old/
A Dddr3_init.c181 u32 ui; in ddr3_restore_and_set_final_windows() local
187 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
188 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); in ddr3_restore_and_set_final_windows()
213 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
238 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
239 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui); in ddr3_save_and_set_training_windows()
A Dddr3_debug.c1443 u32 ui, uj; in print_topology() local
1449 for (ui = 0; ui < MAX_INTERFACE_NUM; ui++) { in print_topology()
1450 VALIDATE_ACTIVE(topology_db->if_act_mask, ui); in print_topology()
1451 printf("\n\tInterface ID: %d\n", ui); in print_topology()
1454 interface_params[ui].memory_freq)); in print_topology()
1461 interface_params[ui].memory_size)); in print_topology()
1465 topology_db->interface_params[ui].cas_l); in print_topology()
1471 topology_db->interface_params[ui]. in print_topology()
1474 topology_db->interface_params[ui]. in print_topology()
1478 interface_params[ui].as_bus_params[uj]. in print_topology()
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/drivers/net/qe/
A Ddm_qe_uec.c74 struct uec_inf *ui = uec->uec_info; in uec_restart_tx() local
77 cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num); in uec_restart_tx()
88 struct uec_inf *ui = uec->uec_info; in uec_restart_rx() local
91 cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num); in uec_restart_rx()

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