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Searched refs:vals (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/uniphier/
A Dclk-uniphier-mio.c46 .vals = { \
A Dclk-uniphier.h37 u32 vals[UNIPHIER_CLK_MUX_MAX_PARENTS]; member
A Dclk-uniphier-core.c52 val |= mux->vals[i]; in uniphier_clk_mux_set_parent()
69 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
/drivers/ddr/marvell/axp/
A Dddr3_init.c792 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()
794 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
795 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
797 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()
A Dddr3_hw_training.h312 MV_DRAM_TRAINING_INIT *vals; member
/drivers/gpio/
A Dgpio-uclass.c1047 int vals[NUM_OPTIONS]; in dm_gpio_get_values_as_int_base3() local
1073 vals[i] = ret; in dm_gpio_get_values_as_int_base3()
1076 log_debug("values: %x %x, count = %d\n", vals[0], vals[1], count); in dm_gpio_get_values_as_int_base3()
1078 uint pd = vals[PULLDOWN] & mask ? 1 : 0; in dm_gpio_get_values_as_int_base3()
1079 uint pu = vals[PULLUP] & mask ? 1 : 0; in dm_gpio_get_values_as_int_base3()

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