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Searched refs:width (Results 1 – 25 of 102) sorted by relevance

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/drivers/clk/meson/
A Dclk_meson.h30 u8 width; member
33 #define PMASK(width) GENMASK(width - 1, 0) argument
34 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
35 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
37 #define PARM_GET(width, shift, reg) \ argument
38 (((reg) & SETPMASK(width, shift)) >> (shift))
39 #define PARM_SET(width, shift, reg, val) \ argument
40 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
A Dg12a.c365 SETPMASK(parm->width, parm->shift), in meson_div_set_rate()
550 SETPMASK(parm->width, parm->shift), in meson_mux_set_parent()
669 n2 = PARM_GET(pn2->width, pn2->shift, reg); in meson_mpll_get_rate()
718 n = PARM_GET(pn->width, pn->shift, reg); in meson_pll_get_rate()
721 m = PARM_GET(pm->width, pm->shift, reg); in meson_pll_get_rate()
724 od = PARM_GET(pod->width, pod->shift, reg); in meson_pll_get_rate()
735 1 << (pfrac->width - 2)); in meson_pll_get_rate()
737 if (frac & BIT(pfrac->width - 1)) in meson_pll_get_rate()
765 n = PARM_GET(pn->width, pn->shift, reg); in meson_pcie_pll_get_rate()
768 m = PARM_GET(pm->width, pm->shift, reg); in meson_pcie_pll_get_rate()
[all …]
/drivers/i2c/muxes/
A Dpca954x.c39 u32 width; member
51 .width = 8,
55 .width = 8,
59 .width = 8,
63 .width = 4,
67 .width = 4,
72 .width = 4,
76 .width = 2,
81 .width = 4,
85 .width = 4,
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/drivers/net/fsl-mc/dpio/
A Dqbman_private.h56 #define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \ argument
57 (uint32_t)((1 << width) - 1))
61 BUG_ON(width > (sizeof(t) * 8)); \
62 return ((uint32_t)val & MAKE_MASK32(width)) << lsoffset; \
66 BUG_ON(width > (sizeof(t) * 8)); \
67 return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
69 static inline uint32_t i32_##t(uint32_t lsoffset, uint32_t width, \
72 BUG_ON(width > (sizeof(t) * 8)); \
73 return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
78 BUG_ON(width > (sizeof(t) * 8)); \
[all …]
A Dqbman_portal.h119 unsigned int width; /* encoding width. (bool must be 1.) */ member
129 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); in qb_attr_code_decode()
137 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) in qb_attr_code_encode()
138 | e32_uint32_t(code->lsoffset, code->width, val); in qb_attr_code_encode()
/drivers/video/
A Dvideo_bmp.c174 if (x < width) { in video_display_rle8_bitmap()
175 if (x + runlen > width) in video_display_rle8_bitmap()
176 cnt = width - x; in video_display_rle8_bitmap()
193 if (x < width) { in video_display_rle8_bitmap()
201 if (x + runlen > width) in video_display_rle8_bitmap()
202 cnt = width - x; in video_display_rle8_bitmap()
313 padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width); in video_bmp_display()
320 if ((x + width) > pwidth) in video_bmp_display()
321 width = pwidth - x; in video_bmp_display()
341 x, y, width, height); in video_bmp_display()
[all …]
A Dsandbox_osd.c14 uint width; member
33 info->width = priv->width; in sandbox_osd_get_info()
49 pos = 2 * (row * priv->width + col); in sandbox_osd_set_mem()
51 if (pos >= 2 * (priv->width * priv->height)) in sandbox_osd_set_mem()
66 priv->width = col; in _sandbox_osd_set_size()
68 size = priv->width * priv->height; in _sandbox_osd_set_size()
97 if (col >= priv->width || row >= priv->height) in sandbox_osd_print()
121 pos = row * priv->width + col; in sandbox_osd_print()
132 uint memsize = 2 * (priv->width * priv->height); in sandbox_osd_get_mem()
A Dconsole_truetype.c282 int width, height, xoff, yoff; in console_truetype_putc_xy() local
434 width, in console_truetype_putc_xy()
746 int width, last_width; in truetype_measure() local
767 width = 0; in truetype_measure()
783 last_width = width; in truetype_measure()
788 neww = width + advance; in truetype_measure()
799 width = last_width; in truetype_measure()
823 width = neww; in truetype_measure()
851 int width; in truetype_nominal() local
859 width = 0; in truetype_nominal()
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A Dsimplefb.c22 u32 width, height, rot; in simple_video_probe() local
44 ret = ofnode_read_u32(node, "width", &width); in simple_video_probe()
46 if (ret || !width || !height) { in simple_video_probe()
52 uc_priv->xsize = width; in simple_video_probe()
A Dconsole_core.c28 debug("width: %d\n", fontdata->width); in console_set_font()
33 vc_priv->x_charsize = fontdata->width; in console_set_font()
36 vc_priv->cols = vid_priv->ysize / fontdata->width; in console_set_font()
40 vc_priv->cols = vid_priv->xsize / fontdata->width; in console_set_font()
97 width_remainder = fontdata->width % 8; in fill_char_vertically()
151 width_remainder = fontdata->width % 8; in fill_char_horizontally()
219 *sizep = priv->fontdata->width; in console_simple_get_font_size()
A Dconsole_rotate.c105 fontdata->width); in console_putc_xy_1()
107 return VID_TO_POS(fontdata->width); in console_putc_xy_1()
189 x - fontdata->width + 1, in console_putc_xy_2()
191 fontdata->width, in console_putc_xy_2()
194 return VID_TO_POS(fontdata->width); in console_putc_xy_2()
280 linenum - fontdata->width + 1, in console_putc_xy_3()
282 fontdata->width); in console_putc_xy_3()
284 return VID_TO_POS(fontdata->width); in console_putc_xy_3()
/drivers/clk/
A Dclk-divider.c54 return val ? val : clk_div_mask(width) + 1; in _get_div()
67 div = _get_div(table, val, flags, width); in divider_recalc_rate()
90 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
93 divider->flags, divider->width); in clk_divider_recalc_rate()
152 value = _get_val(table, div, flags, width); in divider_get_val()
165 divider->width, divider->flags); in clk_divider_set_rate()
188 void __iomem *reg, u8 shift, u8 width, in _register_divider() argument
196 if (width + shift > 16) { in _register_divider()
210 div->width = width; in _register_divider()
233 void __iomem *reg, u8 shift, u8 width, in clk_register_divider() argument
[all …]
A Dclk-mux.c170 void __iomem *reg, u8 shift, u8 width, in clk_register_mux() argument
173 u32 mask = BIT(width) - 1; in clk_register_mux()
179 width = fls(mask) - ffs(mask) + 1; in clk_register_mux()
180 if (width + shift > 16) { in clk_register_mux()
A Dclk_k210.c72 u8 width; member
126 .width = (_width), \
226 u8 width; member
229 #define MUX(id, reg, shift, width) \ argument
257 .width = (_width), \
275 u8 width; member
282 .width = (_width), \
1008 u8 width) in k210_clk_readl() argument
1012 return (reg >> shift) & (BIT(width) - 1); in k210_clk_readl()
1016 u8 width, u32 val) in k210_clk_writel() argument
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/drivers/clk/imx/
A Dclk.h144 u8 shift, u8 width) in imx_clk_divider() argument
147 reg, shift, width, 0); in imx_clk_divider()
156 reg, shift, width, 0); in imx_clk_busy_divider()
161 u8 shift, u8 width) in imx_clk_divider2() argument
165 reg, shift, width, 0); in imx_clk_divider2()
182 width, 0); in imx_clk_mux_flags()
186 void __iomem *reg, u8 shift, u8 width, in imx_clk_mux2_flags() argument
192 reg, shift, width, 0); in imx_clk_mux2_flags()
201 width, 0); in imx_clk_mux()
211 width, 0); in imx_clk_busy_mux()
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/drivers/ram/k3-ddrss/
A Dcps_drv_lpddr4.h78 static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
79 static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value) in cps_fldset() argument
83 if ((width == 1U) && (is_woclr == 0U)) in cps_fldset()
90 static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
91 static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value) in cps_fldclear() argument
95 if ((width == 1U) && (is_woset == 0U)) in cps_fldclear()
/drivers/clk/sophgo/
A Dclk-common.h25 u8 width; member
38 .width = _width, \
61 u32 mask = GENMASK(field->shift + field->width - 1, field->shift); in cv1800b_clk_getfield()
69 u32 mask = GENMASK(field->shift + field->width - 1, field->shift); in cv1800b_clk_setfield()
/drivers/pinctrl/
A Dpinctrl-single.c30 u32 width; member
104 switch (pdata->width) { in single_read()
120 switch (pdata->width) { in single_write()
169 return offset / (pdata->width / BITS_PER_BYTE); in single_get_pin_by_offset()
181 mux_bytes = pdata->width / BITS_PER_BYTE; in single_get_offset_by_pin()
263 mux_bytes = pdata->width / BITS_PER_BYTE; in single_request()
392 npins_in_reg = pdata->width / priv->bits_per_pin; in single_configure_bits()
546 size = pdata->offset + pdata->width / BITS_PER_BYTE; in single_probe()
556 priv->npins = size / (pdata->width / BITS_PER_BYTE); in single_probe()
564 priv->npins *= (pdata->width / priv->bits_per_pin); in single_probe()
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/drivers/clk/microchip/
A Dmpfs_clk_cfg.c47 u8 width; member
77 val &= clk_div_mask(cfg->width); in mpfs_cfg_clk_recalc_rate()
91 divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags); in mpfs_cfg_clk_set_rate()
97 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); in mpfs_cfg_clk_set_rate()
108 .cfg.width = _width, \
/drivers/ddr/altera/
A Dsdram_gen5.c73 const unsigned int width = 8; in get_errata_rows() local
80 debug("workaround rows - width %d\n", width); in get_errata_rows()
85 newrows = lldiv(memsize, cs * (width / 8)); in get_errata_rows()
504 unsigned long row, bank, col, cs, width; in sdram_calculate_size() local
548 width = readl(&sdr_ctrl->dram_if_width); in sdram_calculate_size()
551 if (width == SDRAM_WIDTH_32BIT_WITH_ECC) in sdram_calculate_size()
552 width = 32; in sdram_calculate_size()
553 if (width == SDRAM_WIDTH_16BIT_WITH_ECC) in sdram_calculate_size()
554 width = 16; in sdram_calculate_size()
558 temp = temp * cs * (width / 8); in sdram_calculate_size()
/drivers/video/nexell/
A Ds5pxx18_dp.c204 int width = top->screen_width; in dp_plane_screen_setup() local
211 nx_mlc_set_screen_size(module, width, height); in dp_plane_screen_setup()
224 __func__, module, width, height, in dp_plane_screen_setup()
243 int ex = sx + plane->width - 1; in dp_plane_layer_setup()
263 plane->width * pixel_byte); in dp_plane_layer_setup()
267 __func__, module, layer, plane->width, plane->height, in dp_plane_layer_setup()
271 plane->width * pixel_byte, pixel_byte); in dp_plane_layer_setup()
/drivers/clk/adi/
A Dclk.h71 void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m);
84 void __iomem *reg, u8 shift, u8 width, u8 extra_flags) in cgu_divider() argument
87 reg, shift, width, CLK_DIVIDER_MAX_AT_ZERO | extra_flags); in cgu_divider()
/drivers/net/phy/
A Db53.c627 u8 page, offset, width; in do_b53_reg_read() local
643 width = dectoul(argv[3], NULL); in do_b53_reg_read()
645 switch (width) { in do_b53_reg_read()
672 printf("Unsupported width: %d\n", width); in do_b53_reg_read()
681 u8 page, offset, width; in do_b53_reg_write() local
695 width = dectoul(argv[3], NULL); in do_b53_reg_write()
696 if (width == 48 || width == 64) in do_b53_reg_write()
701 switch (width) { in do_b53_reg_write()
718 printf("Unsupported width: %d\n", width); in do_b53_reg_write()
/drivers/phy/starfive/
A Dphy-jh7110-pcie.c47 unsigned int phy_mode, width, usb3_phy, ss_mode, split; in phy_pcie_mode_set() local
60 width = 0; in phy_pcie_mode_set()
66 width = PCIE_BUS_WIDTH; in phy_pcie_mode_set()
73 regmap_field_write(data->bus_width, width); in phy_pcie_mode_set()
/drivers/clk/exynos/
A Dclk.h81 u8 width; member
96 .width = w, \
124 u8 width; member
136 .width = w, \

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