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Searched refs:CLK_UART0_DIV (Results 1 – 3 of 3) sorted by relevance

/dts/upstream/include/dt-bindings/clock/
A Dpistachio-clk.h67 #define CLK_UART0_DIV 77 macro
A Drk3568-cru.h22 #define CLK_UART0_DIV 9 macro
/dts/upstream/src/mips/img/
A Dpistachio.dtsi260 <&clk_core CLK_UART0_DIV>;

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