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Searched refs:CLK_UART0_INTERNAL_DIV (Results 1 – 2 of 2) sorted by relevance

/dts/upstream/include/dt-bindings/clock/
A Dpistachio-clk.h66 #define CLK_UART0_INTERNAL_DIV 76 macro
/dts/upstream/src/mips/img/
A Dpistachio.dtsi259 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,

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