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Searched refs:GCC_PCIE0_AXI_MASTER_ARES (Results 1 – 6 of 6) sorted by relevance

/dts/upstream/include/dt-bindings/reset/
A Dqcom,gcc-ipq5018.h49 #define GCC_PCIE0_AXI_MASTER_ARES 40 macro
A Dqcom,gcc-ipq6018.h108 #define GCC_PCIE0_AXI_MASTER_ARES 99 macro
/dts/upstream/include/dt-bindings/clock/
A Dqcom,gcc-ipq8074.h358 #define GCC_PCIE0_AXI_MASTER_ARES 120 macro
/dts/upstream/src/arm64/qcom/
A Dipq5018.dtsi606 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
A Dipq8074.dtsi949 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
A Dipq6018.dtsi912 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,

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