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Searched refs:GCC_PCIE0_PHY_BCR (Results 1 – 11 of 11) sorted by relevance

/dts/upstream/include/dt-bindings/reset/
A Dqcom,gcc-ipq5018.h44 #define GCC_PCIE0_PHY_BCR 35 macro
A Dqcom,gcc-ipq6018.h78 #define GCC_PCIE0_PHY_BCR 69 macro
A Dqcom,ipq9574-gcc.h30 #define GCC_PCIE0_PHY_BCR 21 macro
A Dqcom,ipq5424-gcc.h35 #define GCC_PCIE0_PHY_BCR 26 macro
/dts/upstream/Bindings/phy/
A Dqcom,ipq8074-qmp-pcie-phy.yaml98 resets = <&gcc GCC_PCIE0_PHY_BCR>,
/dts/upstream/include/dt-bindings/clock/
A Dqcom,gcc-ipq8074.h316 #define GCC_PCIE0_PHY_BCR 78 macro
/dts/upstream/src/arm64/qcom/
A Dipq5018.dtsi174 resets = <&gcc GCC_PCIE0_PHY_BCR>,
A Dipq8074.dtsi216 resets = <&gcc GCC_PCIE0_PHY_BCR>,
A Dipq5424.dtsi175 resets = <&gcc GCC_PCIE0_PHY_BCR>,
A Dipq6018.dtsi300 resets = <&gcc GCC_PCIE0_PHY_BCR>,
A Dipq9574.dtsi254 resets = <&gcc GCC_PCIE0_PHY_BCR>,

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