Searched refs:PLL4 (Results 1 – 16 of 16) sorted by relevance
| /dts/upstream/include/dt-bindings/clock/ |
| A D | qcom,lcc-ipq806x.h | 9 #define PLL4 0 macro
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| A D | qcom,lcc-msm8960.h | 9 #define PLL4 0 macro
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| A D | stm32mp13-clks.h | 22 #define PLL4 9 macro
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| A D | stm32mp1-clks.h | 186 #define PLL4 179 macro
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| /dts/upstream/Bindings/clock/ |
| A D | qcom,gcc-ipq8064.yaml | 34 - description: PLL4 from LCC
66 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
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| A D | qcom,gcc-mdm9615.yaml | 31 - description: PLL4 from LLC
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| /dts/upstream/Bindings/sound/ |
| A D | ti,j721e-cpb-audio.yaml | 19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
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| A D | ti,j721e-cpb-ivi-audio.yaml | 24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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| /dts/upstream/src/arm/st/ |
| A D | stm32mp157c-odyssey.dts | 41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
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| A D | stm32mp153c-lxa-fairytux2.dtsi | 116 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */
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| A D | stm32mp15xc-lxa-tac.dtsi | 168 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */
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| /dts/upstream/src/arm/qcom/ |
| A D | qcom-mdm9615.dtsi | 108 <&lcc PLL4>;
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| A D | qcom-msm8960.dtsi | 195 <&lcc PLL4>;
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| A D | qcom-ipq8064.dtsi | 501 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
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| A D | qcom-apq8064.dtsi | 721 <&lcc PLL4>;
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| /dts/upstream/src/arm64/ti/ |
| A D | k3-am65-main.dtsi | 1019 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
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