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Searched refs:SCLK_UART0 (Results 1 – 25 of 36) sorted by relevance

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/dts/upstream/include/dt-bindings/clock/
A Drk3036-cru.h23 #define SCLK_UART0 77 macro
A Dexynos7-clk.h79 #define SCLK_UART0 2 macro
A Ds5pv210.h197 #define SCLK_UART0 175 macro
A Drk3188-cru-common.h20 #define SCLK_UART0 64 macro
A Drk3128-cru.h25 #define SCLK_UART0 77 macro
A Drk3228-cru.h24 #define SCLK_UART0 77 macro
A Drk3308-cru.h21 #define SCLK_UART0 17 macro
A Drv1108-cru.h22 #define SCLK_UART0 72 macro
A Drk3288-cru.h32 #define SCLK_UART0 77 macro
A Drk3328-cru.h27 #define SCLK_UART0 38 macro
A Drk3368-cru.h30 #define SCLK_UART0 77 macro
A Drockchip,rk3528-cru.h31 #define SCLK_UART0 19 macro
A Drockchip,rk3576-cru.h158 #define SCLK_UART0 140 macro
A Drockchip,rv1126-cru.h82 #define SCLK_UART0 16 macro
A Drk3399-cru.h38 #define SCLK_UART0 81 macro
A Drockchip,rk3588-cru.h682 #define SCLK_UART0 667 macro
A Drk3568-cru.h24 #define SCLK_UART0 11 macro
/dts/upstream/Bindings/clock/
A Drockchip,rk3528-cru.yaml14 controller for SoC peripherals. For example, it provides SCLK_UART0 and
/dts/upstream/src/arm/rockchip/
A Drk3xxx.dtsi114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
A Drv1126.dtsi452 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
A Drk3036.dtsi543 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
/dts/upstream/src/arm/samsung/
A Ds5pv210.dtsi322 <&clocks SCLK_UART0>;
A Ds5pv210-aries.dtsi881 assigned-clocks = <&clocks MOUT_UART0>, <&clocks SCLK_UART0>;
/dts/upstream/src/arm64/exynos/
A Dexynos7.dtsi287 <&clock_peric0 SCLK_UART0>;
/dts/upstream/src/arm64/rockchip/
A Drk3328.dtsi368 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
831 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,

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