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/dts/upstream/include/dt-bindings/clock/
A Dam3.h9 #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) argument
13 #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) argument
48 #define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) argument
57 #define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) argument
71 #define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) argument
76 #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) argument
84 #define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) argument
89 #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) argument
106 #define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) argument
111 #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) argument
A Dam4.h9 #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) argument
13 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) argument
18 #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) argument
24 #define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) argument
59 #define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) argument
73 #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) argument
78 #define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) argument
127 #define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) argument
132 #define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) argument
137 #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) argument
A Ddra7.h9 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) argument
22 #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) argument
44 #define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) argument
71 #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) argument
119 #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) argument
125 #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) argument
130 #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) argument
165 #define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) argument
175 #define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) argument
197 #define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) argument
A Ddm814.h9 #define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET) argument
39 #define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET) argument
/dts/upstream/Bindings/gpu/host1x/
A Dnvidia,tegra234-nvdec.yaml70 nvidia,bl-manifest-offset:
76 nvidia,bl-code-offset:
82 nvidia,bl-data-offset:
88 nvidia,os-manifest-offset:
94 nvidia,os-code-offset:
100 nvidia,os-data-offset:
115 - nvidia,bl-manifest-offset
116 - nvidia,bl-code-offset
117 - nvidia,bl-data-offset
119 - nvidia,os-code-offset
[all …]
/dts/upstream/src/mips/mti/
A Dsead3.dts100 offset = <0x50>;
115 offset = <0x10>;
121 offset = <0x10>;
127 offset = <0x10>;
133 offset = <0x10>;
139 offset = <0x10>;
145 offset = <0x10>;
151 offset = <0x10>;
157 offset = <0x10>;
164 offset = <0x18>;
[all …]
/dts/upstream/include/dt-bindings/pinctrl/
A Domap.h57 #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) argument
74 #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) argument
76 #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) argument
77 #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) argument
/dts/upstream/Bindings/net/
A Ddavinci_emac.txt10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
/dts/upstream/Bindings/reset/
A Dintel,rcu-gw.yaml23 description: Global reset register offset and bit offset.
26 - description: Register offset
27 - description: Register bit offset
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37 Third cell is bit offset in reset status register.
38 For LGM SoC, reset cell count is 2 as bit offset in
40 3 for legacy SoCs as bit offset differs.
/dts/upstream/include/dt-bindings/gpio/
A Dtegra241-gpio.h32 #define TEGRA241_MAIN_GPIO(port, offset) \ argument
33 ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset))
39 #define TEGRA241_AON_GPIO(port, offset) \ argument
40 ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset))
A Dtegra186-gpio.h41 #define TEGRA186_MAIN_GPIO(port, offset) \ argument
42 ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset)
54 #define TEGRA186_AON_GPIO(port, offset) \ argument
55 ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset)
A Dtegra234-gpio.h45 #define TEGRA234_MAIN_GPIO(port, offset) \ argument
46 ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
56 #define TEGRA234_AON_GPIO(port, offset) \ argument
57 ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
A Dtegra194-gpio.h48 #define TEGRA194_MAIN_GPIO(port, offset) \ argument
49 ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)
58 #define TEGRA194_AON_GPIO(port, offset) \ argument
59 ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)
/dts/upstream/Bindings/arm/hisilicon/controller/
A Dsysctrl.yaml19 offset. In addition, the HiP01 system controller has some specific control
54 smp-offset:
56 offset in sysctrl for notifying slave cpu booting
63 resume-offset:
64 description: offset in sysctrl for notifying cpu0 when resume
67 reboot-offset:
68 description: offset in sysctrl for system reboot
119 smp-offset = <0x31c>;
120 resume-offset = <0x308>;
121 reboot-offset = <0x4>;
[all …]
/dts/upstream/Bindings/mtd/
A Dfsl-upm-nand.txt6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
33 fsl,upm-addr-offset = <16>;
34 fsl,upm-cmd-offset = <8>;
53 fsl,upm-addr-offset = <0x10>;
54 fsl,upm-cmd-offset = <0x08>;
/dts/upstream/Bindings/display/msm/
A Ddsi-phy-10nm.yaml38 qcom,phy-rescode-offset-top:
42 Integer array of offset for pull-up legs rescode for all five lanes.
43 To offset the drive strength from the calibrated value in an increasing
49 qcom,phy-rescode-offset-bot:
53 Integer array of offset for pull-down legs rescode for all five lanes.
54 To offset the drive strength from the calibrated value in a decreasing
64 for the HSTX drive. Use supported levels (mV) to offset the drive level
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
/dts/upstream/Bindings/phy/
A Dstarfive,jh7110-pcie-phy.yaml27 - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
29 The phandle to System Register Controller syscon node and the PHY connect offset
37 - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
38 - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
40 The phandle to System Register Controller syscon node and the offset
41 of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
/dts/upstream/Bindings/regulator/
A Danatop-regulator.yaml21 anatop-reg-offset:
23 description: u32 value representing the anatop MFD register offset.
45 anatop-delay-reg-offset:
47 description: u32 value representing the anatop MFD step time register offset.
59 description: u32 value representing regulator enable bit offset.
67 - anatop-reg-offset
84 anatop-reg-offset = <0x140>;
87 anatop-delay-reg-offset = <0x170>;
/dts/upstream/Bindings/mtd/partitions/
A Dtplink,safeloader-partitions.yaml24 This binding describes partitioning method and defines offset of ASCII
25 based partitions table. That offset is picked at manufacturing process
35 partitions-table-offset:
36 description: Flash offset of partitions table
44 - partitions-table-offset
52 partitions-table-offset = <0x100000>;
/dts/upstream/Bindings/display/
A Dxylon,logicvc-display.yaml153 xylon,layer-base-offset:
159 xylon,layer-buffer-offset:
249 xylon,layer-base-offset = <0>;
250 xylon,layer-buffer-offset = <480>;
259 xylon,layer-base-offset = <2400>;
260 xylon,layer-buffer-offset = <480>;
268 xylon,layer-base-offset = <960>;
269 xylon,layer-buffer-offset = <480>;
277 xylon,layer-base-offset = <480>;
278 xylon,layer-buffer-offset = <480>;
[all …]
/dts/upstream/Bindings/iio/afe/
A Dtemperature-transducer.yaml26 T = (Isense(T) / alpha) + offset
27 T = 1 / (Rsense * alpha) * (V + offset * Rsense * alpha)
64 sense-offset-millicelsius:
66 Temperature offset.
67 This offset is commonly used to convert from Kelvins to degrees Celsius.
68 In that case, sense-offset-millicelsius would be set to <(-273150)>.
101 sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
111 sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
/dts/upstream/Bindings/input/touchscreen/
A Dedt-ft5x06.yaml31 offset-x: true
32 offset-y: true
72 offset:
78 offset-x:
79 description: Same as offset, but applies only to the horizontal position.
85 offset-y:
86 description: Same as offset, but applies only to the vertical position.
/dts/upstream/src/arm/arm/
A Darm-realview-eb.dtsi168 offset = <0x08>;
177 offset = <0x08>;
186 offset = <0x08>;
195 offset = <0x08>;
203 offset = <0x08>;
211 offset = <0x08>;
219 offset = <0x08>;
227 offset = <0x08>;
237 vco-offset = <0x0C>;
245 vco-offset = <0x10>;
[all …]
/dts/upstream/Bindings/hwmon/
A Dnational,lm90.yaml89 temperature-offset-millicelsius:
90 … description: Temperature offset to be added to or subtracted from remote temperature measurements.
132 temperature-offset-millicelsius: false
147 temperature-offset-millicelsius:
170 temperature-offset-millicelsius:
184 temperature-offset-millicelsius:
224 temperature-offset-millicelsius = <4000>;
230 temperature-offset-millicelsius = <750>;
/dts/upstream/Bindings/leds/
A Dregister-bit-led.yaml25 The unit-address is in the form of @<reg addr>,<bit offset>
46 offset:
48 register offset to the register controlling this LED
72 offset = <0x08>;
81 offset = <0x08>;
89 offset = <0x08>;

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