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Searched refs:BIT (Results 1 – 25 of 92) sorted by relevance

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/include/
A Dturris-omnia-mcu-interface.h103 STS_CARD_DET = BIT(4),
116 CTL_LIGHT_RST = BIT(0),
117 CTL_HARD_RST = BIT(1),
123 CTL_BOOTLOADER = BIT(7)
141 FEAT_TRNG = BIT(13),
142 FEAT_CRYPTO = BIT(14),
205 INT_CARD_DET = BIT(0),
206 INT_MSATA_IND = BIT(1),
207 INT_USB30_OVC = BIT(2),
210 INT_SFP_nDET = BIT(5),
[all …]
A Domap3_spi.h14 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
15 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
17 #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
18 #define OMAP3_MCSPI_CHCONF_POL BIT(1)
20 #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
25 #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
29 #define OMAP3_MCSPI_CHCONF_IS BIT(18)
33 #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
34 #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
35 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
[all …]
A Ddwmmc.h65 #define DWMCI_INTMSK_RE BIT(1)
67 #define DWMCI_INTMSK_DTO BIT(3)
72 #define DWMCI_INTMSK_RTO BIT(8)
88 #define DWMCI_CTRL_RESET BIT(0)
91 #define DWMCI_DMA_EN BIT(5)
93 #define DWMCI_IDMAC_EN BIT(25)
102 #define DWMCI_CMD_RW BIT(10)
122 #define DWMCI_BUSY BIT(9)
134 #define DWMCI_IDMAC_CH BIT(4)
135 #define DWMCI_IDMAC_FS BIT(3)
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A Daxp209.h31 #define AXP209_OUTPUT_CTRL_EXTEN BIT(0)
32 #define AXP209_OUTPUT_CTRL_DCDC3 BIT(1)
33 #define AXP209_OUTPUT_CTRL_LDO2 BIT(2)
34 #define AXP209_OUTPUT_CTRL_LDO4 BIT(3)
35 #define AXP209_OUTPUT_CTRL_DCDC2 BIT(4)
36 #define AXP209_OUTPUT_CTRL_LDO3 BIT(6)
43 #define AXP209_VRC_LDO3_EN BIT(3)
44 #define AXP209_VRC_DCDC2_EN BIT(2)
71 #define AXP209_IRQ5_PEK_UP BIT(6)
72 #define AXP209_IRQ5_PEK_DOWN BIT(5)
[all …]
A Dsdhci.h33 #define SDHCI_TRNS_DMA BIT(0)
35 #define SDHCI_TRNS_ACMD12 BIT(2)
36 #define SDHCI_TRNS_READ BIT(4)
37 #define SDHCI_TRNS_MULTI BIT(5)
59 #define SDHCI_CMD_INHIBIT BIT(0)
61 #define SDHCI_DAT_ACTIVE BIT(2)
62 #define SDHCI_DOING_WRITE BIT(8)
63 #define SDHCI_DOING_READ BIT(9)
74 #define SDHCI_CTRL_LED BIT(0)
76 #define SDHCI_CTRL_HISPD BIT(2)
[all …]
A Ddw-i3c.h19 #define DEV_CTRL_ENABLE BIT(31)
20 #define DEV_CTRL_RESUME BIT(30)
21 #define DEV_CTRL_HOT_JOIN_NACK BIT(8)
30 #define COMMAND_PORT_TOC BIT(30)
32 #define COMMAND_PORT_SDAP BIT(27)
33 #define COMMAND_PORT_ROC BIT(26)
36 #define COMMAND_PORT_CP BIT(15)
89 #define RESET_CTRL_SOFT BIT(0)
99 #define INTR_DEFSLV_STAT BIT(10)
107 #define INTR_RX_THLD_STAT BIT(1)
[all …]
A Dfsl_esdhc_imx.h178 #define MIX_CTRL_DDREN BIT(3)
179 #define MIX_CTRL_DTDSEL_READ BIT(4)
180 #define MIX_CTRL_AC23EN BIT(7)
181 #define MIX_CTRL_EXE_TUNE BIT(22)
182 #define MIX_CTRL_SMPCLK_SEL BIT(23)
184 #define MIX_CTRL_FBCLK_SEL BIT(25)
185 #define MIX_CTRL_HS400_EN BIT(26)
186 #define MIX_CTRL_HS400_ES BIT(27)
215 #define ESDHC_FLAG_USDHC BIT(3)
220 #define ESDHC_FLAG_HS200 BIT(8)
[all …]
A Dcadence-nand.h73 #define CTRL_STATUS_INIT_COMP BIT(9)
74 #define CTRL_STATUS_CTRL_BUSY BIT(8)
316 #define CDMA_CF_INT BIT(8)
321 #define CDMA_CF_CONT BIT(9)
323 #define CDMA_CF_DMA_MASTER BIT(10)
326 #define CDMA_CS_COMP BIT(15)
329 #define CDMA_CS_FAIL BIT(14)
331 #define CDMA_CS_ERP BIT(11)
333 #define CDMA_CS_TOUT BIT(10)
340 #define CDMA_CS_UNCE BIT(1)
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A Dmipi_dsi.h25 #define MIPI_DSI_MSG_REQ_ACK BIT(0)
27 #define MIPI_DSI_MSG_USE_LPM BIT(1)
144 #define MIPI_DSI_MODE_VIDEO BIT(0)
146 #define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
152 #define MIPI_DSI_MODE_VIDEO_HSE BIT(4)
154 #define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
156 #define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
158 #define MIPI_DSI_MODE_VIDEO_HSA BIT(7)
160 #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
162 #define MIPI_DSI_MODE_EOT_PACKET BIT(9)
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A Dspi.h23 #define SPI_CS_HIGH BIT(2) /* CS active high */
25 #define SPI_3WIRE BIT(4) /* SI/SO signals shared */
26 #define SPI_LOOP BIT(5) /* loopback mode */
27 #define SPI_SLAVE BIT(6) /* slave mode */
28 #define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */
30 #define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
33 #define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
34 #define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
166 #define SPI_XFER_U_PAGE BIT(4)
167 #define SPI_XFER_STACKED BIT(5)
[all …]
A Dk3-dev.h14 #define LPSC_MODULE_EXISTS BIT(0)
15 #define LPSC_NO_CLOCK_GATING BIT(1)
16 #define LPSC_DEPENDS BIT(2)
17 #define LPSC_HAS_RESET_ISO BIT(3)
18 #define LPSC_HAS_LOCAL_RESET BIT(4)
19 #define LPSC_NO_MODULE_RESET BIT(5)
21 #define PSC_PD_EXISTS BIT(0)
22 #define PSC_PD_ALWAYSON BIT(1)
23 #define PSC_PD_DEPENDS BIT(2)
/include/soc/qcom/
A Dgeni-se.h71 #define FORCE_DEFAULT BIT(0)
81 #define SCLK_CGC_ON BIT(3)
94 #define SER_CLK_EN BIT(0)
148 #define M_RX_IRQ_EN BIT(7)
203 #define RX_LAST BIT(31)
209 #define IO2_DATA_IN BIT(1)
210 #define RX_DATA_IN BIT(0)
214 #define TX_EOT BIT(1)
215 #define TX_SBE BIT(2)
220 #define RX_EOT BIT(1)
[all …]
/include/net/pfe_eth/pfe/cbus/
A Demac.h33 #define EMAC_IEVENT_HBERR BIT(31)
34 #define EMAC_IEVENT_BABR BIT(30)
35 #define EMAC_IEVENT_BABT BIT(29)
36 #define EMAC_IEVENT_GRA BIT(28)
37 #define EMAC_IEVENT_TXF BIT(27)
38 #define EMAC_IEVENT_TXB BIT(26)
39 #define EMAC_IEVENT_RXF BIT(25)
40 #define EMAC_IEVENT_RXB BIT(24)
41 #define EMAC_IEVENT_MII BIT(23)
42 #define EMAC_IEVENT_EBERR BIT(22)
[all …]
A Dhif.h36 #define HIF_CTRL_DMA_EN BIT(0)
44 #define HIF_INT_EN BIT(0)
45 #define HIF_RXBD_INT_EN BIT(1)
46 #define HIF_RXPKT_INT_EN BIT(2)
47 #define HIF_TXBD_INT_EN BIT(3)
48 #define HIF_TXPKT_INT_EN BIT(4)
59 #define BD_CTRL_LIFM BIT(18)
60 #define BD_CTRL_LAST_BD BIT(19)
61 #define BD_CTRL_DIR BIT(20)
62 #define BD_CTRL_PKT_XFER BIT(24)
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A Dclass_csr.h159 #define TWO_LEVEL_ROUTE BIT(0)
160 #define PHYNO_IN_HASH BIT(1)
161 #define HW_ROUTE_FETCH BIT(3)
162 #define HW_BRIDGE_FETCH BIT(5)
163 #define IP_ALIGNED BIT(6)
164 #define ARC_HIT_CHECK_EN BIT(7)
165 #define CLASS_TOE BIT(11)
166 #define HASH_CRC_PORT BIT(12)
167 #define HASH_CRC_IP BIT(13)
169 #define QB2BUS_LE BIT(15)
[all …]
/include/linux/usb/
A Dxhci-fsl.h16 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
17 #define USB3_PHY_RX_POWERON BIT(14)
18 #define USB3_PHY_TX_POWERON BIT(15)
27 #define USBOTGSS_WRAPRESET BIT(17)
28 #define USBOTGSS_DMADISABLE BIT(16)
29 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
30 #define USBOTGSS_STANDBYMODE_SMRT BIT(5)
32 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
33 #define USBOTGSS_IDLEMODE_SMRT BIT(3)
37 #define USBOTGSS_COREIRQ_EN BIT(1)
[all …]
A Dphy-rockchip-usbdp.h21 #define DP_SINK_HPD_CFG BIT(11)
22 #define DP_SINK_HPD_SEL BIT(10)
23 #define DP_AUX_DIN_SEL BIT(9)
24 #define DP_AUX_DOUT_SEL BIT(8)
33 #define CMN_DP_LANE_EN_N(n) BIT(n)
41 #define CMN_DP_TX_LANE_SWAP_EN BIT(2)
44 #define CMN_ROPLL_SSC_EN BIT(1)
45 #define CMN_LCPLL_SSC_EN BIT(0)
56 #define CMN_DP_INIT_RSTN BIT(3)
57 #define CMN_DP_CMN_RSTN BIT(2)
[all …]
/include/power/
A Dstpmic1.h21 #define STPMIC1_SWOFF BIT(0)
22 #define STPMIC1_RREQ_EN BIT(1)
31 #define STPMIC1_BUCK_ENA BIT(0)
32 #define STPMIC1_BUCK_PREG_MODE BIT(1)
44 #define STPMIC1_VREF_ENA BIT(0)
47 #define STPMIC1_LDO_ENA BIT(0)
52 #define STPMIC1_LDO3_MODE BIT(7)
59 #define STPMIC1_BST_ON BIT(0)
60 #define STPMIC1_VBUSOTG_ON BIT(1)
61 #define STPMIC1_SWOUT_ON BIT(2)
[all …]
A Dtps65218.h68 #define TPS65218_CC_STAT (BIT(0) | BIT(1))
69 #define TPS65218_STATE (BIT(2) | BIT(3))
70 #define TPS65218_PB_STATE BIT(4)
71 #define TPS65218_AC_STATE BIT(5)
72 #define TPS65218_EE BIT(6)
73 #define TPS65218_FSEAL BIT(7)
/include/linux/mtd/
A Dspi-nor.h17 #define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1))
165 #define SR_E_ERR BIT(5)
166 #define SR_P_ERR BIT(6)
183 #define SR2_QUAD_EN_BIT7 BIT(7)
186 #define SR3_WPS BIT(2)
302 SNOR_F_USE_FSR = BIT(0),
303 SNOR_F_HAS_SR_TB = BIT(1),
307 SNOR_F_USE_CLSR = BIT(5),
308 SNOR_F_BROKEN_RESET = BIT(6),
309 SNOR_F_SOFT_RESET = BIT(7),
[all …]
/include/renesas/
A Drzg2l-pfc.h12 #define PIN_CFG_IOLH_A BIT(0)
13 #define PIN_CFG_IOLH_B BIT(1)
14 #define PIN_CFG_SR BIT(2)
15 #define PIN_CFG_IEN BIT(3)
16 #define PIN_CFG_PUPD BIT(4)
17 #define PIN_CFG_IO_VMC_SD0 BIT(5)
18 #define PIN_CFG_IO_VMC_SD1 BIT(6)
22 #define PIN_CFG_FILONOFF BIT(10)
23 #define PIN_CFG_FILNUM BIT(11)
24 #define PIN_CFG_FILCLKSEL BIT(12)
[all …]
/include/linux/
A Dclk-provider.h51 #define CLK_OPS_PARENT_ENABLE BIT(12)
53 #define CLK_DUTY_CYCLE_PARENT BIT(13)
55 #define CLK_MUX_INDEX_ONE BIT(0)
56 #define CLK_MUX_INDEX_BIT BIT(1)
57 #define CLK_MUX_HIWORD_MASK BIT(2)
59 #define CLK_MUX_ROUND_CLOSEST BIT(4)
111 #define CLK_GATE_SET_TO_DISABLE BIT(0)
112 #define CLK_GATE_HIWORD_MASK BIT(1)
140 #define CLK_DIVIDER_ONE_BASED BIT(0)
142 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
[all …]
/include/test/
A Dtest.h85 UTF_SCAN_PDATA = BIT(0), /* test needs platform data */
86 UTF_PROBE_TEST = BIT(1), /* probe test uclass */
87 UTF_SCAN_FDT = BIT(2), /* scan device tree */
88 UTF_FLAT_TREE = BIT(3), /* test needs flat DT */
89 UTF_LIVE_TREE = BIT(4), /* needs live device tree */
90 UTF_CONSOLE = BIT(5), /* needs console recording */
92 UTF_DM = BIT(6),
93 UTF_OTHER_FDT = BIT(7), /* read in other device tree */
99 UTF_MANUAL = BIT(8),
103 UTF_INIT = BIT(12), /* test inits a suite */
[all …]
/include/linux/soc/ti/
A Dti_sci_protocol.h349 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
351 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
353 #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
355 #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
357 #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
359 #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
430 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
431 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
439 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
455 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
[all …]
/include/linux/mfd/syscon/
A Datmel-matrix.h97 #define AT91_MATRIX_RCB(x) BIT(x)
100 #define AT91_MATRIX_DBPUC BIT(8)
101 #define AT91_MATRIX_DBPDC BIT(9)
102 #define AT91_MATRIX_VDDIOMSEL BIT(16)
105 #define AT91_MATRIX_EBI_IOSR BIT(17)
106 #define AT91_MATRIX_DDR_IOSR BIT(18)
107 #define AT91_MATRIX_NFD0_SELECT BIT(24)
108 #define AT91_MATRIX_DDR_MP_EN BIT(25)
110 #define AT91_MATRIX_USBPUCR_PUON BIT(30)

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