1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #ifndef __ASSEMBLY__ 17 #include <linux/stringify.h> 18 #endif 19 20 /* 21 * Only possible on E500 Version 2 or newer cores. 22 */ 23 24 #define CFG_SYS_CCSRBAR 0xe0000000 25 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR 26 27 /* DDR Setup */ 28 29 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 30 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 31 32 /* I2C addresses of SPD EEPROMs */ 33 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 34 35 /* Make sure required options are set */ 36 #ifndef CONFIG_SPD_EEPROM 37 #error ("CONFIG_SPD_EEPROM is required") 38 #endif 39 40 /* 41 * Physical Address Map 42 * 43 * 32bit: 44 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 45 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 46 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 47 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 48 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 49 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 50 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 51 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 52 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 53 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 54 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 55 * 56 * 36bit: 57 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 58 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 59 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 60 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 61 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 62 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 63 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 64 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 65 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 66 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 67 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 68 * 69 */ 70 71 /* 72 * Local Bus Definitions 73 */ 74 75 /* 76 * FLASH on the Local Bus 77 * Two banks, 8M each, using the CFI driver. 78 * Boot from BR0/OR0 bank at 0xff00_0000 79 * Alternate BR1/OR1 bank at 0xff80_0000 80 * 81 * BR0, BR1: 82 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 83 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 84 * Port Size = 16 bits = BRx[19:20] = 10 85 * Use GPCM = BRx[24:26] = 000 86 * Valid = BRx[31] = 1 87 * 88 * 0 4 8 12 16 20 24 28 89 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 90 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 91 * 92 * OR0, OR1: 93 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 94 * Reserved ORx[17:18] = 11, confusion here? 95 * CSNT = ORx[20] = 1 96 * ACS = half cycle delay = ORx[21:22] = 11 97 * SCY = 6 = ORx[24:27] = 0110 98 * TRLX = use relaxed timing = ORx[29] = 1 99 * EAD = use external address latch delay = OR[31] = 1 100 * 101 * 0 4 8 12 16 20 24 28 102 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 103 */ 104 105 #define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 106 #ifdef CONFIG_PHYS_64BIT 107 #define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull 108 #else 109 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE 110 #endif 111 112 #define CFG_SYS_FLASH_BANKS_LIST \ 113 {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS} 114 115 /* 116 * SDRAM on the Local Bus 117 */ 118 #define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 119 #ifdef CONFIG_PHYS_64BIT 120 #define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 121 #else 122 #define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE 123 #endif 124 #define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 125 126 /* 127 * Base Register 2 and Option Register 2 configure SDRAM. 128 * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 129 * 130 * For BR2, need: 131 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 132 * port-size = 32-bits = BR2[19:20] = 11 133 * no parity checking = BR2[21:22] = 00 134 * SDRAM for MSEL = BR2[24:26] = 011 135 * Valid = BR[31] = 1 136 * 137 * 0 4 8 12 16 20 24 28 138 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 139 * 140 * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 141 * FIXME: the top 17 bits of BR2. 142 */ 143 144 /* 145 * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64. 146 * 147 * For OR2, need: 148 * 64MB mask for AM, OR2[0:7] = 1111 1100 149 * XAM, OR2[17:18] = 11 150 * 9 columns OR2[19-21] = 010 151 * 13 rows OR2[23-25] = 100 152 * EAD set for extra time OR[31] = 1 153 * 154 * 0 4 8 12 16 20 24 28 155 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 156 */ 157 158 #define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 159 #define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 160 #define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 161 #define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 162 163 /* 164 * Common settings for all Local Bus SDRAM commands. 165 * At run time, either BSMA1516 (for CPU 1.1) 166 * or BSMA1617 (for CPU 1.0) (old) 167 * is OR'ed in too. 168 */ 169 #define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 170 | LSDMR_PRETOACT7 \ 171 | LSDMR_ACTTORW7 \ 172 | LSDMR_BL8 \ 173 | LSDMR_WRC4 \ 174 | LSDMR_CL3 \ 175 | LSDMR_RFEN \ 176 ) 177 178 /* 179 * The CADMUS registers are connected to CS3 on CDS. 180 * The new memory map places CADMUS at 0xf8000000. 181 * 182 * For BR3, need: 183 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 184 * port-size = 8-bits = BR[19:20] = 01 185 * no parity checking = BR[21:22] = 00 186 * GPMC for MSEL = BR[24:26] = 000 187 * Valid = BR[31] = 1 188 * 189 * 0 4 8 12 16 20 24 28 190 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 191 * 192 * For OR3, need: 193 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 194 * disable buffer ctrl OR[19] = 0 195 * CSNT OR[20] = 1 196 * ACS OR[21:22] = 11 197 * XACS OR[23] = 1 198 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 199 * SETA OR[28] = 0 200 * TRLX OR[29] = 1 201 * EHTR OR[30] = 1 202 * EAD extra time OR[31] = 1 203 * 204 * 0 4 8 12 16 20 24 28 205 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 206 */ 207 208 #define CADMUS_BASE_ADDR 0xf8000000 209 #ifdef CONFIG_PHYS_64BIT 210 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 211 #else 212 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 213 #endif 214 215 #define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 216 #define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 217 218 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 219 220 #define CFG_SYS_BAUDRATE_TABLE \ 221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 222 223 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) 224 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) 225 226 /* 227 * I2C 228 */ 229 #if !CONFIG_IS_ENABLED(DM_I2C) 230 #define CFG_SYS_I2C_NOPROBES { {0, 0x69} } 231 #endif 232 233 /* 234 * General PCI 235 * Memory space is mapped 1-1, but I/O space must start from 0. 236 */ 237 #define CFG_SYS_PCI1_MEM_VIRT 0x80000000 238 #ifdef CONFIG_PHYS_64BIT 239 #define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull 240 #else 241 #define CFG_SYS_PCI1_MEM_PHYS 0x80000000 242 #endif 243 #define CFG_SYS_PCI1_IO_VIRT 0xe2000000 244 #ifdef CONFIG_PHYS_64BIT 245 #define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull 246 #else 247 #define CFG_SYS_PCI1_IO_PHYS 0xe2000000 248 #endif 249 250 #ifdef CONFIG_PCIE1 251 #define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000 252 #ifdef CONFIG_PHYS_64BIT 253 #define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 254 #else 255 #define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000 256 #endif 257 #define CFG_SYS_PCIE1_IO_VIRT 0xe3000000 258 #ifdef CONFIG_PHYS_64BIT 259 #define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 260 #else 261 #define CFG_SYS_PCIE1_IO_PHYS 0xe3000000 262 #endif 263 #endif 264 265 /* 266 * RapidIO MMU 267 */ 268 #define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000 269 #ifdef CONFIG_PHYS_64BIT 270 #define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 271 #else 272 #define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000 273 #endif 274 #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 275 276 /* 277 * Miscellaneous configurable options 278 */ 279 280 /* 281 * For booting Linux, the board info and command line data 282 * have to be in the first 64 MB of memory, since this is 283 * the maximum mapped by the Linux kernel during initialization. 284 */ 285 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 286 287 /* 288 * Environment Configuration 289 */ 290 291 #define CFG_EXTRA_ENV_SETTINGS \ 292 "hwconfig=fsl_ddr:ecc=off\0" \ 293 "netdev=eth0\0" \ 294 "uboot=" CONFIG_UBOOTPATH "\0" \ 295 "tftpflash=tftpboot $loadaddr $uboot; " \ 296 "protect off " __stringify(CONFIG_TEXT_BASE) \ 297 " +$filesize; " \ 298 "erase " __stringify(CONFIG_TEXT_BASE) \ 299 " +$filesize; " \ 300 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \ 301 " $filesize; " \ 302 "protect on " __stringify(CONFIG_TEXT_BASE) \ 303 " +$filesize; " \ 304 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \ 305 " $filesize\0" \ 306 "consoledev=ttyS1\0" \ 307 "ramdiskaddr=2000000\0" \ 308 "ramdiskfile=ramdisk.uboot\0" \ 309 "fdtaddr=1e00000\0" \ 310 "fdtfile=mpc8548cds.dtb\0" 311 312 #endif /* __CONFIG_H */ 313