1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Ilko Iliev <www.ronetix.at> 7 * 8 * Configuation settings for the RONETIX PM9261 board. 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 19 #include <asm/hardware.h> 20 /* ARM asynchronous clock */ 21 22 #define MASTER_PLL_DIV 15 23 #define MASTER_PLL_MUL 162 24 #define MAIN_PLL_DIV 2 25 #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 26 #define CFG_SYS_AT91_MAIN_CLOCK 18432000 27 28 /* clocks */ 29 /* CKGR_MOR - enable main osc. */ 30 #define CFG_SYS_MOR_VAL \ 31 (AT91_PMC_MOR_MOSCEN | \ 32 (255 << 8)) /* Main Oscillator Start-up Time */ 33 #define CFG_SYS_PLLAR_VAL \ 34 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 35 AT91_PMC_PLLXR_OUT(3) | \ 36 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 37 38 /* PCK/2 = MCK Master Clock from PLLA */ 39 #define CFG_SYS_MCKR1_VAL \ 40 (AT91_PMC_MCKR_CSS_SLOW | \ 41 AT91_PMC_MCKR_PRES_1 | \ 42 AT91_PMC_MCKR_MDIV_2) 43 44 /* PCK/2 = MCK Master Clock from PLLA */ 45 #define CFG_SYS_MCKR2_VAL \ 46 (AT91_PMC_MCKR_CSS_PLLA | \ 47 AT91_PMC_MCKR_PRES_1 | \ 48 AT91_PMC_MCKR_MDIV_2) 49 50 /* define PDC[31:16] as DATA[31:16] */ 51 #define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000 52 /* no pull-up for D[31:16] */ 53 #define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 54 55 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ 56 #define CFG_SYS_MATRIX_EBICSA_VAL \ 57 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) 58 59 /* SDRAM */ 60 /* SDRAMC_MR Mode register */ 61 #define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL 62 /* SDRAMC_TR - Refresh Timer register */ 63 #define CFG_SYS_SDRC_TR_VAL1 0x13C 64 /* SDRAMC_CR - Configuration register*/ 65 #define CFG_SYS_SDRC_CR_VAL \ 66 (AT91_SDRAMC_NC_9 | \ 67 AT91_SDRAMC_NR_13 | \ 68 AT91_SDRAMC_NB_4 | \ 69 AT91_SDRAMC_CAS_3 | \ 70 AT91_SDRAMC_DBW_32 | \ 71 (1 << 8) | /* Write Recovery Delay */ \ 72 (7 << 12) | /* Row Cycle Delay */ \ 73 (3 << 16) | /* Row Precharge Delay */ \ 74 (2 << 20) | /* Row to Column Delay */ \ 75 (5 << 24) | /* Active to Precharge Delay */ \ 76 (1 << 28)) /* Exit Self Refresh to Active Delay */ 77 78 /* Memory Device Register -> SDRAM */ 79 #define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 80 #define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 81 #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 82 #define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 83 #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 84 #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 85 #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 86 #define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 87 #define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 88 #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 89 #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 90 #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 91 #define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 92 #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 93 #define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 94 #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 95 #define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 96 #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 97 98 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 99 #define CFG_SYS_SMC0_SETUP0_VAL \ 100 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 101 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 102 #define CFG_SYS_SMC0_PULSE0_VAL \ 103 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 104 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 105 #define CFG_SYS_SMC0_CYCLE0_VAL \ 106 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 107 #define CFG_SYS_SMC0_MODE0_VAL \ 108 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 109 AT91_SMC_MODE_DBW_16 | \ 110 AT91_SMC_MODE_TDF | \ 111 AT91_SMC_MODE_TDF_CYCLE(6)) 112 113 /* user reset enable */ 114 #define CFG_SYS_RSTC_RMR_VAL \ 115 (AT91_RSTC_KEY | \ 116 AT91_RSTC_CR_PROCRST | \ 117 AT91_RSTC_MR_ERSTL(1) | \ 118 AT91_RSTC_MR_ERSTL(2)) 119 120 /* Disable Watchdog */ 121 #define CFG_SYS_WDTC_WDMR_VAL \ 122 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 123 AT91_WDT_MR_WDV(0xfff) | \ 124 AT91_WDT_MR_WDDIS | \ 125 AT91_WDT_MR_WDD(0xfff)) 126 127 /* SDRAM */ 128 #define PHYS_SDRAM 0x20000000 129 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 130 131 /* NAND flash */ 132 #define CFG_SYS_NAND_BASE 0x40000000 133 /* our ALE is AD22 */ 134 #define CFG_SYS_NAND_MASK_ALE (1 << 22) 135 /* our CLE is AD21 */ 136 #define CFG_SYS_NAND_MASK_CLE (1 << 21) 137 #define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 138 #define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) 139 140 /* NOR flash */ 141 #define PHYS_FLASH_1 0x10000000 142 #define CFG_SYS_FLASH_BASE PHYS_FLASH_1 143 144 /* USB */ 145 #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 146 147 #define CFG_EXTRA_ENV_SETTINGS \ 148 "partition=nand0,0\0" \ 149 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 150 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 151 "fbcon=rotate:3 " \ 152 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 153 "addip=setenv bootargs $(bootargs) " \ 154 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 155 ":$(hostname):eth0:off\0" \ 156 "ramboot=tftpboot 0x22000000 vmImage;" \ 157 "run ramargs;run addip;bootm 22000000\0" \ 158 "nfsboot=tftpboot 0x22000000 vmImage;" \ 159 "run nfsargs;run addip;bootm 22000000\0" \ 160 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 161 "" 162 163 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM 164 165 #endif 166