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Searched refs:CFG_SYS_SDRAM_BASE (Results 1 – 25 of 385) sorted by relevance

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/include/configs/
A Dexynos78x0-common.h24 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
27 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
29 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
31 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
33 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
35 #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
37 #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
39 #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
41 #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
43 #define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
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A Dexynos7420-common.h22 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
24 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
26 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
28 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
30 #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
32 #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
34 #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
36 #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
A Dsmdkv310.h14 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
28 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
30 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
32 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
A Dexynos5-common.h30 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
32 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
34 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
36 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
38 #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
40 #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
42 #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
44 #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
A Dboston.h25 # define CFG_SYS_SDRAM_BASE 0xffffffff80000000 macro
27 # define CFG_SYS_SDRAM_BASE 0x80000000 macro
A Dmalta.h22 # define CFG_SYS_SDRAM_BASE 0xffffffff80000000 macro
24 # define CFG_SYS_SDRAM_BASE 0x80000000 macro
A Darbel.h9 #define CFG_SYS_SDRAM_BASE 0x0 macro
12 #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
A Dorigen.h14 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
15 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
A Drk3576_common.h15 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
17 #define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE)
A Dsmdkc100.h19 #define CFG_SYS_SDRAM_BASE 0x30000000 macro
80 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
A Dgazerbeam.h15 #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ macro
17 #define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
A Dthunderx_88xx.h16 #define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0)
33 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
A Diot_devkit.h53 #define CFG_SYS_SDRAM_BASE DCCM_BASE macro
62 CFG_SYS_SDRAM_BASE) - \
A DM5272C3.h64 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
73 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
91 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
A DM5275EVB.h74 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
83 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
100 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
A Dstmark2.h59 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
72 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
86 #define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
A DM5208EVBE.h55 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
68 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
93 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
A Dodroid.h21 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
23 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
A Ds5pc210_universal.h17 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
18 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
A Dimx93_var_som.h14 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
30 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
A DM5249EVB.h55 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
68 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
91 #define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
A DM5282EVB.h67 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
78 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
98 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
A DM53017EVB.h69 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
82 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
A DM5235EVB.h66 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
75 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
103 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
A DM5329EVB.h63 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
76 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \

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