1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007-2013 Tensilica, Inc. 4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <asm/arch/core.h> 11 #include <asm/addrspace.h> 12 #include <asm/config.h> 13 14 /* 15 * The 'xtfpga' board describes a set of very similar boards with only minimal 16 * differences. 17 */ 18 19 /*===================*/ 20 /* RAM Layout */ 21 /*===================*/ 22 23 #if XCHAL_HAVE_PTP_MMU 24 #define CFG_SYS_MEMORY_BASE \ 25 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) 26 #define CFG_SYS_IO_BASE 0xf0000000 27 #else 28 #define CFG_SYS_MEMORY_BASE 0x60000000 29 #define CFG_SYS_IO_BASE 0x90000000 30 #define CFG_MAX_MEM_MAPPED 0x10000000 31 #endif 32 33 /* Onboard RAM sizes: 34 * 35 * LX60 0x04000000 64 MB 36 * LX110 0x03000000 48 MB 37 * LX200 0x06000000 96 MB 38 * ML605 0x18000000 384 MB 39 * KC705 0x38000000 896 MB 40 * 41 * noMMU configurations can only see first 256MB of onboard memory. 42 */ 43 44 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 45 #define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE 46 #else 47 #define CFG_SYS_SDRAM_SIZE 0x10000000 48 #endif 49 50 #define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000) 51 52 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ 53 54 /* Memory test is destructive so default must not overlap vectors or U-Boot*/ 55 56 #if defined(CFG_MAX_MEM_MAPPED) && \ 57 CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE 58 #define XTENSA_SYS_TEXT_ADDR \ 59 (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) 60 #else 61 #define XTENSA_SYS_TEXT_ADDR \ 62 (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) 63 #endif 64 65 /*==============================*/ 66 /* U-Boot general configuration */ 67 /*==============================*/ 68 69 /* Console I/O Buffer Size */ 70 /*==============================*/ 71 /* U-Boot autoboot configuration */ 72 /*==============================*/ 73 74 /*=========================================*/ 75 /* FPGA Registers (board info and control) */ 76 /*=========================================*/ 77 78 /* 79 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier 80 * releases may not provide any/all of these registers or at these offsets. 81 * Some of the FPGA registers are broken down into bitfields described by 82 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. 83 */ 84 85 /* FPGA core clock frequency in Hz (also input to UART) */ 86 #define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ 87 88 /* 89 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): 90 * Bits 0..5 set the lower 6 bits of the default ethernet MAC. 91 * Bit 6 is reserved for future use by Tensilica. 92 * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to 93 * the base of flash * (when on/1) or to the base of RAM (when off/0). 94 */ 95 #define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) 96 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ 97 #define FPGAREG_MAC_WIDTH 6 98 #define FPGAREG_MAC_MASK 0x3f 99 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ 100 #define FPGAREG_BOOT_WIDTH 1 101 #define FPGAREG_BOOT_MASK 0x80 102 #define FPGAREG_BOOT_RAM 0 103 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) 104 105 /* Force hard reset of board by writing a code to this register */ 106 #define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ 107 #define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ 108 109 /*====================*/ 110 /* Serial Driver Info */ 111 /*====================*/ 112 113 #define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ 114 115 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ 116 #define CFG_SYS_NS16550_CLK get_board_sys_clk() 117 118 /*======================*/ 119 /* Ethernet Driver Info */ 120 /*======================*/ 121 122 #define CFG_ETHBASE 00:50:C2:13:6f:00 123 #define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000) 124 #define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) 125 126 /*=====================*/ 127 /* Flash & Environment */ 128 /*=====================*/ 129 130 #ifdef CONFIG_XTFPGA_LX60 131 # define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ 132 # define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ 133 # define CFG_SYS_FLASH_BASE IOADDR(0x08000000) 134 #elif defined(CONFIG_XTFPGA_KC705) 135 # define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ 136 # define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 137 # define CFG_SYS_FLASH_BASE IOADDR(0x00000000) 138 #else 139 # define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ 140 # define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 141 # define CFG_SYS_FLASH_BASE IOADDR(0x08000000) 142 #endif 143 144 /* 145 * Put environment in top block (64kB) 146 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB 147 */ 148 149 /* print 'E' for empty sector on flinfo */ 150 151 #endif /* __CONFIG_H */ 152