1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2015 Google, Inc 4 * Copyright 2014 Rockchip Inc. 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 7 */ 8 9 #ifndef _DW_HDMI_H 10 #define _DW_HDMI_H 11 12 #define HDMI_EDID_BLOCK_SIZE 128 13 14 /* Identification Registers */ 15 #define HDMI_DESIGN_ID 0x0000 16 #define HDMI_REVISION_ID 0x0001 17 #define HDMI_PRODUCT_ID0 0x0002 18 #define HDMI_PRODUCT_ID1 0x0003 19 #define HDMI_CONFIG0_ID 0x0004 20 #define HDMI_CONFIG1_ID 0x0005 21 #define HDMI_CONFIG2_ID 0x0006 22 #define HDMI_CONFIG3_ID 0x0007 23 24 /* Interrupt Registers */ 25 #define HDMI_IH_FC_STAT0 0x0100 26 #define HDMI_IH_FC_STAT1 0x0101 27 #define HDMI_IH_FC_STAT2 0x0102 28 #define HDMI_IH_AS_STAT0 0x0103 29 #define HDMI_IH_PHY_STAT0 0x0104 30 #define HDMI_IH_I2CM_STAT0 0x0105 31 #define HDMI_IH_CEC_STAT0 0x0106 32 #define HDMI_IH_VP_STAT0 0x0107 33 #define HDMI_IH_I2CMPHY_STAT0 0x0108 34 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109 35 36 #define HDMI_IH_MUTE_FC_STAT0 0x0180 37 #define HDMI_IH_MUTE_FC_STAT1 0x0181 38 #define HDMI_IH_MUTE_FC_STAT2 0x0182 39 #define HDMI_IH_MUTE_AS_STAT0 0x0183 40 #define HDMI_IH_MUTE_PHY_STAT0 0x0184 41 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185 42 #define HDMI_IH_MUTE_CEC_STAT0 0x0186 43 #define HDMI_IH_MUTE_VP_STAT0 0x0187 44 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 45 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 46 #define HDMI_IH_MUTE 0x01FF 47 48 /* Video Sample Registers */ 49 #define HDMI_TX_INVID0 0x0200 50 #define HDMI_TX_INSTUFFING 0x0201 51 #define HDMI_TX_GYDATA0 0x0202 52 #define HDMI_TX_GYDATA1 0x0203 53 #define HDMI_TX_RCRDATA0 0x0204 54 #define HDMI_TX_RCRDATA1 0x0205 55 #define HDMI_TX_BCBDATA0 0x0206 56 #define HDMI_TX_BCBDATA1 0x0207 57 58 /* Video Packetizer Registers */ 59 #define HDMI_VP_STATUS 0x0800 60 #define HDMI_VP_PR_CD 0x0801 61 #define HDMI_VP_STUFF 0x0802 62 #define HDMI_VP_REMAP 0x0803 63 #define HDMI_VP_CONF 0x0804 64 #define HDMI_VP_STAT 0x0805 65 #define HDMI_VP_INT 0x0806 66 #define HDMI_VP_MASK 0x0807 67 #define HDMI_VP_POL 0x0808 68 69 /* Frame Composer Registers */ 70 #define HDMI_FC_INVIDCONF 0x1000 71 #define HDMI_FC_INHACTV0 0x1001 72 #define HDMI_FC_INHACTV1 0x1002 73 #define HDMI_FC_INHBLANK0 0x1003 74 #define HDMI_FC_INHBLANK1 0x1004 75 #define HDMI_FC_INVACTV0 0x1005 76 #define HDMI_FC_INVACTV1 0x1006 77 #define HDMI_FC_INVBLANK 0x1007 78 #define HDMI_FC_HSYNCINDELAY0 0x1008 79 #define HDMI_FC_HSYNCINDELAY1 0x1009 80 #define HDMI_FC_HSYNCINWIDTH0 0x100A 81 #define HDMI_FC_HSYNCINWIDTH1 0x100B 82 #define HDMI_FC_VSYNCINDELAY 0x100C 83 #define HDMI_FC_VSYNCINWIDTH 0x100D 84 #define HDMI_FC_INFREQ0 0x100E 85 #define HDMI_FC_INFREQ1 0x100F 86 #define HDMI_FC_INFREQ2 0x1010 87 #define HDMI_FC_CTRLDUR 0x1011 88 #define HDMI_FC_EXCTRLDUR 0x1012 89 #define HDMI_FC_EXCTRLSPAC 0x1013 90 #define HDMI_FC_CH0PREAM 0x1014 91 #define HDMI_FC_CH1PREAM 0x1015 92 #define HDMI_FC_CH2PREAM 0x1016 93 #define HDMI_FC_AVICONF3 0x1017 94 #define HDMI_FC_GCP 0x1018 95 #define HDMI_FC_AVICONF0 0x1019 96 #define HDMI_FC_AVICONF1 0x101A 97 #define HDMI_FC_AVICONF2 0x101B 98 #define HDMI_FC_AVIVID 0x101C 99 #define HDMI_FC_AVIETB0 0x101D 100 #define HDMI_FC_AVIETB1 0x101E 101 #define HDMI_FC_AVISBB0 0x101F 102 #define HDMI_FC_AVISBB1 0x1020 103 #define HDMI_FC_AVIELB0 0x1021 104 #define HDMI_FC_AVIELB1 0x1022 105 #define HDMI_FC_AVISRB0 0x1023 106 #define HDMI_FC_AVISRB1 0x1024 107 #define HDMI_FC_AUDICONF0 0x1025 108 #define HDMI_FC_AUDICONF1 0x1026 109 #define HDMI_FC_AUDICONF2 0x1027 110 #define HDMI_FC_AUDICONF3 0x1028 111 #define HDMI_FC_VSDIEEEID0 0x1029 112 #define HDMI_FC_VSDSIZE 0x102A 113 114 /* HDMI Source PHY Registers */ 115 #define HDMI_PHY_CONF0 0x3000 116 #define HDMI_PHY_TST0 0x3001 117 #define HDMI_PHY_TST1 0x3002 118 #define HDMI_PHY_TST2 0x3003 119 #define HDMI_PHY_STAT0 0x3004 120 #define HDMI_PHY_INT0 0x3005 121 #define HDMI_PHY_MASK0 0x3006 122 #define HDMI_PHY_POL0 0x3007 123 124 /* HDMI Master PHY Registers */ 125 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 126 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 127 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 128 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 129 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 130 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 131 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 132 #define HDMI_PHY_I2CM_INT_ADDR 0x3027 133 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 134 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029 135 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a 136 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b 137 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c 138 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d 139 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e 140 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f 141 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 142 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 143 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 144 145 /* Audio Sampler Registers */ 146 #define HDMI_AUD_CONF0 0x3100 147 #define HDMI_AUD_CONF1 0x3101 148 #define HDMI_AUD_INT 0x3102 149 #define HDMI_AUD_CONF2 0x3103 150 #define HDMI_AUD_INT1 0x3104 151 #define HDMI_AUD_N1 0x3200 152 #define HDMI_AUD_N2 0x3201 153 #define HDMI_AUD_N3 0x3202 154 #define HDMI_AUD_CTS1 0x3203 155 #define HDMI_AUD_CTS2 0x3204 156 #define HDMI_AUD_CTS3 0x3205 157 #define HDMI_AUD_INPUTCLKFS 0x3206 158 #define HDMI_AUD_SPDIFINT 0x3302 159 #define HDMI_AUD_CONF0_HBR 0x3400 160 #define HDMI_AUD_HBR_STATUS 0x3401 161 #define HDMI_AUD_HBR_INT 0x3402 162 #define HDMI_AUD_HBR_POL 0x3403 163 #define HDMI_AUD_HBR_MASK 0x3404 164 165 /* Main Controller Registers */ 166 #define HDMI_MC_SFRDIV 0x4000 167 #define HDMI_MC_CLKDIS 0x4001 168 #define HDMI_MC_SWRSTZ 0x4002 169 #define HDMI_MC_OPCTRL 0x4003 170 #define HDMI_MC_FLOWCTRL 0x4004 171 #define HDMI_MC_PHYRSTZ 0x4005 172 #define HDMI_MC_LOCKONCLOCK 0x4006 173 #define HDMI_MC_HEACPHY_RST 0x4007 174 175 /* Color Space Converter Registers */ 176 #define HDMI_CSC_CFG 0x4100 177 #define HDMI_CSC_SCALE 0x4101 178 #define HDMI_CSC_COEF_A1_MSB 0x4102 179 #define HDMI_CSC_COEF_A1_LSB 0x4103 180 #define HDMI_CSC_COEF_A2_MSB 0x4104 181 #define HDMI_CSC_COEF_A2_LSB 0x4105 182 #define HDMI_CSC_COEF_A3_MSB 0x4106 183 #define HDMI_CSC_COEF_A3_LSB 0x4107 184 #define HDMI_CSC_COEF_A4_MSB 0x4108 185 #define HDMI_CSC_COEF_A4_LSB 0x4109 186 #define HDMI_CSC_COEF_B1_MSB 0x410A 187 #define HDMI_CSC_COEF_B1_LSB 0x410B 188 #define HDMI_CSC_COEF_B2_MSB 0x410C 189 #define HDMI_CSC_COEF_B2_LSB 0x410D 190 #define HDMI_CSC_COEF_B3_MSB 0x410E 191 #define HDMI_CSC_COEF_B3_LSB 0x410F 192 #define HDMI_CSC_COEF_B4_MSB 0x4110 193 #define HDMI_CSC_COEF_B4_LSB 0x4111 194 #define HDMI_CSC_COEF_C1_MSB 0x4112 195 #define HDMI_CSC_COEF_C1_LSB 0x4113 196 #define HDMI_CSC_COEF_C2_MSB 0x4114 197 #define HDMI_CSC_COEF_C2_LSB 0x4115 198 #define HDMI_CSC_COEF_C3_MSB 0x4116 199 #define HDMI_CSC_COEF_C3_LSB 0x4117 200 #define HDMI_CSC_COEF_C4_MSB 0x4118 201 #define HDMI_CSC_COEF_C4_LSB 0x4119 202 203 /* I2C Master Registers (E-DDC) */ 204 #define HDMI_I2CM_SLAVE 0x7E00 205 #define HDMI_I2CM_ADDRESS 0x7E01 206 #define HDMI_I2CM_DATAO 0x7E02 207 #define HDMI_I2CM_DATAI 0x7E03 208 #define HDMI_I2CM_OPERATION 0x7E04 209 #define HDMI_I2CM_INT 0x7E05 210 #define HDMI_I2CM_CTLINT 0x7E06 211 #define HDMI_I2CM_DIV 0x7E07 212 #define HDMI_I2CM_SEGADDR 0x7E08 213 #define HDMI_I2CM_SOFTRSTZ 0x7E09 214 #define HDMI_I2CM_SEGPTR 0x7E0A 215 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B 216 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C 217 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D 218 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E 219 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F 220 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 221 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 222 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 223 #define HDMI_I2CM_BUF0 0x7E20 224 225 enum { 226 /* HDMI PHY registers define */ 227 PHY_OPMODE_PLLCFG = 0x06, 228 PHY_CKCALCTRL = 0x05, 229 PHY_CKSYMTXCTRL = 0x09, 230 PHY_VLEVCTRL = 0x0e, 231 PHY_PLLCURRCTRL = 0x10, 232 PHY_PLLPHBYCTRL = 0x13, 233 PHY_PLLGMPCTRL = 0x15, 234 PHY_PLLCLKBISTPHASE = 0x17, 235 PHY_TXTERM = 0x19, 236 237 /* ih_phy_stat0 field values */ 238 HDMI_IH_PHY_STAT0_HPD = 0x1, 239 240 /* ih_mute field values */ 241 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, 242 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 243 244 /* tx_invid0 field values */ 245 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, 246 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, 247 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, 248 249 /* tx_instuffing field values */ 250 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, 251 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, 252 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 253 254 /* vp_pr_cd field values */ 255 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, 256 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, 257 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, 258 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, 259 260 /* vp_stuff field values */ 261 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, 262 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, 263 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, 264 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, 265 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, 266 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, 267 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 268 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 269 270 /* vp_conf field values */ 271 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, 272 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, 273 HDMI_VP_CONF_PP_EN_ENMASK = 0x20, 274 HDMI_VP_CONF_PP_EN_DISABLE = 0x00, 275 HDMI_VP_CONF_PR_EN_MASK = 0x10, 276 HDMI_VP_CONF_PR_EN_DISABLE = 0x00, 277 HDMI_VP_CONF_YCC422_EN_MASK = 0x8, 278 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, 279 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, 280 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, 281 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, 282 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, 283 284 /* vp_remap field values */ 285 HDMI_VP_REMAP_YCC422_16BIT = 0x0, 286 287 /* fc_invidconf field values */ 288 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, 289 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, 290 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, 291 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, 292 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, 293 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 294 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, 295 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, 296 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 297 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, 298 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, 299 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, 300 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, 301 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, 302 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, 303 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, 304 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, 305 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, 306 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, 307 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, 308 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, 309 310 /* fc_aviconf0-fc_aviconf3 field values */ 311 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, 312 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, 313 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, 314 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, 315 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, 316 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, 317 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, 318 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, 319 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, 320 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, 321 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, 322 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, 323 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, 324 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, 325 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, 326 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, 327 328 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, 329 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, 330 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, 331 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, 332 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, 333 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, 334 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, 335 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, 336 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, 337 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, 338 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, 339 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, 340 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, 341 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, 342 343 HDMI_FC_AVICONF2_SCALING_MASK = 0x03, 344 HDMI_FC_AVICONF2_SCALING_NONE = 0x00, 345 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, 346 HDMI_FC_AVICONF2_SCALING_VERT = 0x02, 347 HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, 348 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, 349 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, 350 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, 351 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, 352 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, 353 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, 354 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, 355 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, 356 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, 357 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, 358 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, 359 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, 360 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, 361 362 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, 363 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, 364 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, 365 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, 366 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, 367 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, 368 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, 369 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, 370 371 /* fc_gcp field values*/ 372 HDMI_FC_GCP_SET_AVMUTE = 0x02, 373 HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, 374 375 /* phy_conf0 field values */ 376 HDMI_PHY_CONF0_PDZ_MASK = 0x80, 377 HDMI_PHY_CONF0_PDZ_OFFSET = 7, 378 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, 379 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, 380 HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, 381 HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, 382 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, 383 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, 384 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, 385 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, 386 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, 387 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, 388 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, 389 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, 390 391 /* phy_tst0 field values */ 392 HDMI_PHY_TST0_TSTCLR_MASK = 0x20, 393 HDMI_PHY_TST0_TSTCLR_OFFSET = 5, 394 395 /* phy_stat0 field values */ 396 HDMI_PHY_HPD = 0x02, 397 HDMI_PHY_TX_PHY_LOCK = 0x01, 398 399 /* phy_i2cm_slave_addr field values */ 400 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, 401 402 /* phy_i2cm_operation_addr field values */ 403 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, 404 405 /* hdmi_phy_i2cm_int_addr */ 406 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, 407 408 /* hdmi_phy_i2cm_ctlint_addr */ 409 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, 410 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, 411 412 /* aud_conf0 field values */ 413 HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, 414 HDMI_AUD_CONF0_I2S_SELECT = 0x20, 415 HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, 416 HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, 417 HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, 418 HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, 419 420 /* aud_conf0 field values */ 421 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, 422 HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, 423 424 /* aud_n3 field values */ 425 HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, 426 HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, 427 428 /* aud_cts3 field values */ 429 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, 430 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, 431 HDMI_AUD_CTS3_N_SHIFT_1 = 0, 432 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, 433 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, 434 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, 435 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, 436 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, 437 HDMI_AUD_CTS3_CTS_MANUAL = 0x10, 438 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, 439 440 /* aud_inputclkfs filed values */ 441 HDMI_AUD_INPUTCLKFS_128 = 0x0, 442 443 /* mc_clkdis field values */ 444 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, 445 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, 446 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, 447 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, 448 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, 449 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, 450 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, 451 452 /* mc_swrstz field values */ 453 HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, 454 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, 455 456 /* mc_flowctrl field values */ 457 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, 458 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, 459 460 /* mc_phyrstz field values */ 461 HDMI_MC_PHYRSTZ_ASSERT = 0x0, 462 HDMI_MC_PHYRSTZ_DEASSERT = 0x1, 463 464 /* mc_heacphy_rst field values */ 465 HDMI_MC_HEACPHY_RST_ASSERT = 0x1, 466 467 /* i2cm filed values */ 468 HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, 469 HDMI_I2CM_SEGADDR_DDC = 0x30, 470 HDMI_I2CM_OP_RD8_EXT = 0x2, 471 HDMI_I2CM_OP_RD8 = 0x1, 472 HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, 473 HDMI_I2CM_DIV_FAST_MODE = 0x8, 474 HDMI_I2CM_DIV_STD_MODE = 0x0, 475 HDMI_I2CM_SOFTRSTZ_MASK = 0x1, 476 477 /* CSC_CFG field values */ 478 HDMI_CSC_CFG_INTMODE_MASK = 0x30, 479 HDMI_CSC_CFG_INTMODE_OFFSET = 4, 480 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, 481 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, 482 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, 483 HDMI_CSC_CFG_DECMODE_MASK = 0x3, 484 HDMI_CSC_CFG_DECMODE_OFFSET = 0, 485 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, 486 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, 487 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, 488 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, 489 490 /* CSC_SCALE field values */ 491 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, 492 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, 493 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, 494 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, 495 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, 496 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, 497 }; 498 499 struct hdmi_mpll_config { 500 u64 mpixelclock; 501 /* Mode of Operation and PLL Dividers Control Register */ 502 u32 cpce; 503 /* PLL Gmp Control Register */ 504 u32 gmp; 505 /* PLL Current Control Register */ 506 u32 curr; 507 }; 508 509 struct hdmi_phy_config { 510 u64 mpixelclock; 511 u32 sym_ctr; /* clock symbol and transmitter control */ 512 u32 term; /* transmission termination value */ 513 u32 vlev_ctr; /* voltage level control */ 514 }; 515 516 struct hdmi_vmode { 517 bool mdataenablepolarity; 518 519 unsigned int mpixelclock; 520 unsigned int mpixelrepetitioninput; 521 unsigned int mpixelrepetitionoutput; 522 }; 523 524 struct hdmi_data_info { 525 unsigned int enc_in_bus_format; 526 unsigned int enc_out_bus_format; 527 unsigned int enc_in_encoding; 528 unsigned int enc_out_encoding; 529 unsigned int pix_repet_factor; 530 unsigned int hdcp_enable; 531 struct hdmi_vmode video_mode; 532 }; 533 534 struct dw_hdmi; 535 536 struct dw_hdmi_phy_ops { 537 int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); 538 void (*read_hpd)(struct dw_hdmi *hdmi, bool hdp_status); 539 void (*setup_hpd)(struct dw_hdmi *hdmi); 540 }; 541 542 struct dw_hdmi { 543 ulong ioaddr; 544 const struct hdmi_mpll_config *mpll_cfg; 545 const struct hdmi_phy_config *phy_cfg; 546 u8 i2c_clk_high; 547 u8 i2c_clk_low; 548 u8 reg_io_width; 549 struct hdmi_data_info hdmi_data; 550 struct udevice *ddc_bus; 551 const struct dw_hdmi_phy_ops *ops; 552 553 void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); 554 u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); 555 }; 556 557 int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); 558 int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); 559 void dw_hdmi_phy_init(struct dw_hdmi *hdmi); 560 561 int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); 562 int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); 563 void dw_hdmi_init(struct dw_hdmi *hdmi); 564 int dw_hdmi_detect_hpd(struct dw_hdmi *hdmi); 565 566 #endif 567