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/include/linux/
A Dlog2.h27 int __ilog2_u32(u32 n) in __ilog2_u32() argument
29 return fls(n) - 1; in __ilog2_u32()
35 int __ilog2_u64(u64 n) in __ilog2_u64() argument
37 return fls64(n) - 1; in __ilog2_u64()
52 return (n != 0 && ((n & (n - 1)) == 0)); in is_power_of_2()
85 #define ilog2(n) \ argument
88 (n) < 2 ? 0 : \
154 __ilog2_u64(n) \
168 (n == 1) ? 1 : \
192 return n > 1 ? ilog2(n - 1) + 1 : 0; in __order_base_2()
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A Dbuild_bug.h19 #define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \ argument
20 BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
21 #define BUILD_BUG_ON_NOT_POWER_OF_2(n) \ argument
22 BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
A Dioport.h139 #define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0) argument
140 #define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (n… argument
141 #define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0) argument
148 resource_size_t n,
152 #define release_region(start,n) __release_region(&ioport_resource, (start), (n)) argument
153 #define check_mem_region(start,n) __check_region(&iomem_resource, (start), (n)) argument
154 #define release_mem_region(start,n) __release_region(&iomem_resource, (start), (n)) argument
161 resource_size_t n) in check_region() argument
163 return __check_region(&ioport_resource, s, n); in check_region()
175 resource_size_t n, const char *name);
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A Dlist.h410 pos = n, n = pos->next)
421 pos = n, n = pos->prev)
516 pos = n, n = list_entry(n->member.next, typeof(*n), member))
532 pos = n, n = list_entry(n->member.next, typeof(*n), member))
547 pos = n, n = list_entry(n->member.next, typeof(*n), member))
563 pos = n, n = list_entry(n->member.prev, typeof(*n), member))
625 __hlist_del(n); in hlist_del()
644 h->first = n; in hlist_add_head()
653 n->next = next; in hlist_add_before()
655 *(n->pprev) = n; in hlist_add_before()
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A Dpsci.h28 #define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) argument
32 #define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) argument
A Drbtree.h88 #define rbtree_postorder_for_each_entry_safe(pos, n, root, field) \ argument
90 pos && ({ n = rb_entry_safe(rb_next_postorder(&pos->field), \
92 pos = n)
A Dkernel.h31 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) argument
108 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) argument
114 #define lower_32_bits(n) ((u32)(n)) argument
/include/
A Dfm_eth.h81 .num = n - 1, \
83 .port = FM##idx##_DTSEC##n, \
95 .num = n - 1, \
97 .port = FM##idx##_10GEC##n, \
109 .num = n - 1, \
111 .port = FM##idx##_10GEC##n, \
122 .num = n - 1, \
124 .port = FM##idx##_10GEC##n, \
138 .num = n - 1, \
153 .num = n - 1, \
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A Dfsl_ifc.h203 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) argument
207 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) argument
217 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) argument
219 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) argument
235 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) argument
254 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) argument
264 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) argument
266 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) argument
268 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) argument
270 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) argument
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A Ddiv64.h28 # define do_div(n,base) ({ \ argument
31 __rem = ((u64)(n)) % __base; \
32 (n) = ((u64)(n)) / __base; \
164 u32 n_lo = n; in __arch_xprod_64()
165 u32 n_hi = n >> 32; in __arch_xprod_64()
204 # define do_div(n,base) ({ \ argument
211 (n) >>= ilog2(__base); \
215 u32 __res_lo, __n_lo = (n); \
216 (n) = __div64_const32(n, __base); \
218 __res_lo = (n); \
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A Dppc_asm.tmpl139 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
140 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
141 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
142 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
143 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
144 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
145 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
146 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
147 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
148 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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A Dk3_bist.h26 #define TISCI_BIT(n) ((1) << (n)) argument
A Dphysmem.h21 phys_addr_t arch_phys_memset(phys_addr_t s, int c, phys_size_t n);
A Dlibata.h434 #define ata_id_u32(id,n) \ argument
435 (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
436 #define ata_id_u64(id,n) \ argument
437 ( ((u64) (id)[(n) + 3] << 48) | \
438 ((u64) (id)[(n) + 2] << 32) | \
439 ((u64) (id)[(n) + 1] << 16) | \
440 ((u64) (id)[(n) + 0]) )
/include/renesas/
A Drzg2l-pfc.h43 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) argument
72 #define P(n) (0x0000 + 0x10 + (n)) argument
73 #define PM(n) (0x0100 + 0x20 + (n) * 2) argument
74 #define PMC(n) (0x0200 + 0x10 + (n)) argument
75 #define PFC(n) (0x0400 + 0x40 + (n) * 4) argument
76 #define PIN(n) (0x0800 + 0x10 + (n)) argument
77 #define IOLH(n) (0x1000 + (n) * 8) argument
78 #define IEN(n) (0x1800 + (n) * 8) argument
80 #define SD_CH(n) (0x3000 + (n) * 4) argument
/include/power/
A Das3722.h15 #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) argument
16 #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) argument
23 #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) argument
/include/linux/usb/
A Dphy-rockchip-usbdp.h25 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) argument
32 #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) argument
33 #define CMN_DP_LANE_EN_N(n) BIT(n) argument
61 #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ argument
A Ddwc3.h156 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) argument
164 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) argument
165 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) argument
170 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) argument
176 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) argument
204 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) argument
205 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) argument
214 #define GFLADJ_30MHZ(n) ((n) & 0x3f) argument
/include/linux/clk/
A Dat91_pmc.h63 #define AT91_PMC_PLL_UPDT_STUPTIM(n) ((n) << 16) /* Startup time */ argument
87 #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) argument
89 #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) argument
155 #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) argument
157 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ argument
185 #define AT91_PMC_FSTT(n) BIT(n) argument
229 #define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) argument
232 #define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) argument
238 #define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) argument
241 #define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) argument
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/include/soc/qcom/
A Drpmh.h15 const struct tcs_cmd *cmd, u32 n);
20 const struct tcs_cmd *cmd, u32 n) in rpmh_write() argument
26 #define rpmh_write_async(dev, state, cmd, n) rpmh_write(dev, state, cmd, n) argument
/include/dt-bindings/mrc/
A Dquark.h37 #define DRAM_RANK(n) (1 << (n)) argument
40 #define DRAM_CHANNEL(n) (1 << (n)) argument
/include/dm/
A Ddevres.h185 size_t n, size_t size, gfp_t flags) in devm_kmalloc_array() argument
187 if (size != 0 && n > SIZE_MAX / size) in devm_kmalloc_array()
189 return devm_kmalloc(dev, n * size, flags); in devm_kmalloc_array()
193 size_t n, size_t size, gfp_t flags) in devm_kcalloc() argument
195 return devm_kmalloc_array(dev, n, size, flags | __GFP_ZERO); in devm_kcalloc()
267 size_t n, size_t size, gfp_t flags) in devm_kmalloc_array() argument
269 return kmalloc_array(n, size, flags); in devm_kmalloc_array()
273 size_t n, size_t size, gfp_t flags) in devm_kcalloc() argument
275 return kcalloc(n, size, flags); in devm_kcalloc()
/include/env/phytec/
A Drauc.env15 test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1";
16 test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3;
17 test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3;
42 if test -n "${raucstatus}"; then
/include/crypto/internal/
A Drsa.h32 const u8 *n; member
/include/xen/interface/
A Dmemory.h314 #define XENMEM_resource_ioreq_server_frame_ioreq(n) (1 + (n)) argument

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