1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
4 */
5
6 #include <clock_legacy.h>
7 #include <log.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <mach/ar71xx_regs.h>
13 #include <mach/ath79.h>
14 #include <wait_bit.h>
15
16 #define PLL_SRIF_DPLL2_KI_LSB 29
17 #define PLL_SRIF_DPLL2_KI_MASK 0x60000000
18 #define PLL_SRIF_DPLL2_KI_SET(x) \
19 (((x) << PLL_SRIF_DPLL2_KI_LSB) & PLL_SRIF_DPLL2_KI_MASK)
20 #define PLL_SRIF_DPLL2_KD_LSB 25
21 #define PLL_SRIF_DPLL2_KD_MASK 0x1e000000
22 #define PLL_SRIF_DPLL2_KD_SET(x) \
23 (((x) << PLL_SRIF_DPLL2_KD_LSB) & PLL_SRIF_DPLL2_KD_MASK)
24 #define PLL_SRIF_DPLL2_PLL_PWD_LSB 22
25 #define PLL_SRIF_DPLL2_PLL_PWD_MASK 0x00400000
26 #define PLL_SRIF_DPLL2_PLL_PWD_SET(x) \
27 (((x) << PLL_SRIF_DPLL2_PLL_PWD_LSB) & PLL_SRIF_DPLL2_PLL_PWD_MASK)
28 #define PLL_SRIF_DPLL2_OUTDIV_LSB 19
29 #define PLL_SRIF_DPLL2_OUTDIV_MASK 0x00380000
30 #define PLL_SRIF_DPLL2_OUTDIV_SET(x) \
31 (((x) << PLL_SRIF_DPLL2_OUTDIV_LSB) & PLL_SRIF_DPLL2_OUTDIV_MASK)
32 #define PLL_SRIF_DPLL2_PHASE_SHIFT_LSB 12
33 #define PLL_SRIF_DPLL2_PHASE_SHIFT_MASK 0x0007f000
34 #define PLL_SRIF_DPLL2_PHASE_SHIFT_SET(x) \
35 (((x) << PLL_SRIF_DPLL2_PHASE_SHIFT_LSB) & PLL_SRIF_DPLL2_PHASE_SHIFT_MASK)
36 #define CPU_PLL_CONFIG_PLLPWD_LSB 30
37 #define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
38 #define CPU_PLL_CONFIG_PLLPWD_SET(x) \
39 (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
40 #define CPU_PLL_CONFIG_OUTDIV_LSB 19
41 #define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
42 #define CPU_PLL_CONFIG_OUTDIV_SET(x) \
43 (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
44 #define CPU_PLL_CONFIG_RANGE_LSB 17
45 #define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
46 #define CPU_PLL_CONFIG_RANGE_SET(x) \
47 (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
48 #define CPU_PLL_CONFIG_REFDIV_LSB 12
49 #define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
50 #define CPU_PLL_CONFIG_REFDIV_SET(x) \
51 (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
52 #define CPU_PLL_CONFIG1_NINT_LSB 18
53 #define CPU_PLL_CONFIG1_NINT_MASK 0x07fc0000
54 #define CPU_PLL_CONFIG1_NINT_SET(x) \
55 (((x) << CPU_PLL_CONFIG1_NINT_LSB) & CPU_PLL_CONFIG1_NINT_MASK)
56 #define CPU_PLL_DITHER1_DITHER_EN_LSB 31
57 #define CPU_PLL_DITHER1_DITHER_EN_MASK 0x80000000
58 #define CPU_PLL_DITHER1_DITHER_EN_SET(x) \
59 (((x) << CPU_PLL_DITHER1_DITHER_EN_LSB) & CPU_PLL_DITHER1_DITHER_EN_MASK)
60 #define CPU_PLL_DITHER1_UPDATE_COUNT_LSB 24
61 #define CPU_PLL_DITHER1_UPDATE_COUNT_MASK 0x3f000000
62 #define CPU_PLL_DITHER1_UPDATE_COUNT_SET(x) \
63 (((x) << CPU_PLL_DITHER1_UPDATE_COUNT_LSB) & CPU_PLL_DITHER1_UPDATE_COUNT_MASK)
64 #define CPU_PLL_DITHER1_NFRAC_STEP_LSB 18
65 #define CPU_PLL_DITHER1_NFRAC_STEP_MASK 0x00fc0000
66 #define CPU_PLL_DITHER1_NFRAC_STEP_SET(x) \
67 (((x) << CPU_PLL_DITHER1_NFRAC_STEP_LSB) & CPU_PLL_DITHER1_NFRAC_STEP_MASK)
68 #define CPU_PLL_DITHER1_NFRAC_MIN_LSB 0
69 #define CPU_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff
70 #define CPU_PLL_DITHER1_NFRAC_MIN_SET(x) \
71 (((x) << CPU_PLL_DITHER1_NFRAC_MIN_LSB) & CPU_PLL_DITHER1_NFRAC_MIN_MASK)
72 #define CPU_PLL_DITHER2_NFRAC_MAX_LSB 0
73 #define CPU_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff
74 #define CPU_PLL_DITHER2_NFRAC_MAX_SET(x) \
75 (((x) << CPU_PLL_DITHER2_NFRAC_MAX_LSB) & CPU_PLL_DITHER2_NFRAC_MAX_MASK)
76 #define DDR_PLL_CONFIG_PLLPWD_LSB 30
77 #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
78 #define DDR_PLL_CONFIG_PLLPWD_SET(x) \
79 (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
80 #define DDR_PLL_CONFIG_OUTDIV_LSB 23
81 #define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
82 #define DDR_PLL_CONFIG_OUTDIV_SET(x) \
83 (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
84 #define DDR_PLL_CONFIG_RANGE_LSB 21
85 #define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
86 #define DDR_PLL_CONFIG_RANGE_SET(x) \
87 (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
88 #define DDR_PLL_CONFIG_REFDIV_LSB 16
89 #define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
90 #define DDR_PLL_CONFIG_REFDIV_SET(x) \
91 (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
92 #define DDR_PLL_CONFIG1_NINT_LSB 18
93 #define DDR_PLL_CONFIG1_NINT_MASK 0x07fc0000
94 #define DDR_PLL_CONFIG1_NINT_SET(x) \
95 (((x) << DDR_PLL_CONFIG1_NINT_LSB) & DDR_PLL_CONFIG1_NINT_MASK)
96 #define DDR_PLL_DITHER1_DITHER_EN_LSB 31
97 #define DDR_PLL_DITHER1_DITHER_EN_MASK 0x80000000
98 #define DDR_PLL_DITHER1_DITHER_EN_SET(x) \
99 (((x) << DDR_PLL_DITHER1_DITHER_EN_LSB) & DDR_PLL_DITHER1_DITHER_EN_MASK)
100 #define DDR_PLL_DITHER1_UPDATE_COUNT_LSB 27
101 #define DDR_PLL_DITHER1_UPDATE_COUNT_MASK 0x78000000
102 #define DDR_PLL_DITHER1_UPDATE_COUNT_SET(x) \
103 (((x) << DDR_PLL_DITHER1_UPDATE_COUNT_LSB) & DDR_PLL_DITHER1_UPDATE_COUNT_MASK)
104 #define DDR_PLL_DITHER1_NFRAC_STEP_LSB 20
105 #define DDR_PLL_DITHER1_NFRAC_STEP_MASK 0x07f00000
106 #define DDR_PLL_DITHER1_NFRAC_STEP_SET(x) \
107 (((x) << DDR_PLL_DITHER1_NFRAC_STEP_LSB) & DDR_PLL_DITHER1_NFRAC_STEP_MASK)
108 #define DDR_PLL_DITHER1_NFRAC_MIN_LSB 0
109 #define DDR_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff
110 #define DDR_PLL_DITHER1_NFRAC_MIN_SET(x) \
111 (((x) << DDR_PLL_DITHER1_NFRAC_MIN_LSB) & DDR_PLL_DITHER1_NFRAC_MIN_MASK)
112 #define DDR_PLL_DITHER2_NFRAC_MAX_LSB 0
113 #define DDR_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff
114 #define DDR_PLL_DITHER2_NFRAC_MAX_SET(x) \
115 (((x) << DDR_PLL_DITHER2_NFRAC_MAX_LSB) & DDR_PLL_DITHER2_NFRAC_MAX_MASK)
116 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
117 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
118 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) \
119 (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
120 #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB 21
121 #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK 0x00200000
122 #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x) \
123 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)
124 #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB 20
125 #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK 0x00100000
126 #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x) \
127 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)
128 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
129 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
130 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) \
131 (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
132 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
133 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
134 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) \
135 (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
136 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
137 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
138 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) \
139 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
140 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
141 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
142 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) \
143 (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
144 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
145 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
146 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) \
147 (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
148 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
149 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
150 #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) \
151 (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
152
153 #define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1f)
154 #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)
155 #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)
156 #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)
157 #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)
158 #define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \
159 CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \
160 CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \
161 CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)
162 #define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)
163 #define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)
164 #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)
165 #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)
166 #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)
167 #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)
168 #define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \
169 DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \
170 DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \
171 DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)
172 #define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)
173 #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
174 #define CPU_AND_DDR_CLK_FROM_DDR \
175 CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)
176 #define CPU_AND_DDR_CLK_FROM_CPU \
177 CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)
178 #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL \
179 CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)
180 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV \
181 CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
182 #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV \
183 CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
184
set_val(u32 _reg,u32 _mask,u32 _val)185 static inline void set_val(u32 _reg, u32 _mask, u32 _val)
186 {
187 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
188 AR71XX_PLL_SIZE, MAP_NOCACHE);
189 writel((readl(pll_regs + _reg) & (~(_mask))) | _val, pll_regs + _reg);
190 }
191
192 #define cpu_pll_set(_mask, _val) \
193 set_val(QCA956X_PLL_CPU_CONFIG_REG, _mask, _val)
194
195 #define ddr_pll_set(_mask, _val) \
196 set_val(QCA956X_PLL_DDR_CONFIG_REG, _mask, _val)
197
198 #define cpu_ddr_control_set(_mask, _val) \
199 set_val(QCA956X_PLL_CLK_CTRL_REG, _mask, _val)
200
201 DECLARE_GLOBAL_DATA_PTR;
202
qca956x_get_xtal(void)203 static u32 qca956x_get_xtal(void)
204 {
205 u32 val;
206
207 val = ath79_get_bootstrap();
208 if (val & QCA956X_BOOTSTRAP_REF_CLK_40)
209 return 40000000;
210 else
211 return 25000000;
212 }
213
get_serial_clock(void)214 int get_serial_clock(void)
215 {
216 return qca956x_get_xtal();
217 }
218
qca956x_pll_init(void)219 void qca956x_pll_init(void)
220 {
221 void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE,
222 QCA956X_SRIF_SIZE, MAP_NOCACHE);
223 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
224 AR71XX_PLL_SIZE, MAP_NOCACHE);
225
226 /* 8.16.2 Baseband DPLL2 */
227 writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
228 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_OUTDIV_SET(1) |
229 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_BB_DPLL2_REG);
230
231 /* 8.16.2 PCIE DPLL2 */
232 writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
233 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_OUTDIV_SET(3) |
234 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_PCIE_DPLL2_REG);
235
236 /* 8.16.2 DDR DPLL2 */
237 writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
238 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6),
239 srif_regs + QCA956X_SRIF_DDR_DPLL2_REG);
240
241 /* 8.16.2 CPU DPLL2 */
242 writel(PLL_SRIF_DPLL2_KI_SET(1) | PLL_SRIF_DPLL2_KD_SET(7) |
243 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6),
244 srif_regs + QCA956X_SRIF_CPU_DPLL2_REG);
245
246 /* pll_bypass_set */
247 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
248 CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
249 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
250 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
251 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
252 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
253
254 /* init_cpu_pll */
255 cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(1));
256 cpu_pll_set(CPU_PLL_CONFIG_REFDIV_MASK, CPU_PLL_CONFIG_REF_DIV_VAL);
257 cpu_pll_set(CPU_PLL_CONFIG_RANGE_MASK, CPU_PLL_CONFIG_RANGE_VAL);
258 cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL1);
259 set_val(QCA956X_PLL_CPU_CONFIG1_REG, CPU_PLL_CONFIG1_NINT_MASK, \
260 CPU_PLL_CONFIG1_NINT_VAL);
261
262 /* init_ddr_pll */
263 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(1));
264 ddr_pll_set(DDR_PLL_CONFIG_REFDIV_MASK, DDR_PLL_CONFIG_REF_DIV_VAL);
265 ddr_pll_set(DDR_PLL_CONFIG_RANGE_MASK, DDR_PLL_CONFIG_RANGE_VAL);
266 ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL1);
267 set_val(QCA956X_PLL_DDR_CONFIG1_REG, DDR_PLL_CONFIG1_NINT_MASK,
268 DDR_PLL_CONFIG1_NINT_VAL);
269
270 /* init_ahb_pll */
271 writel(CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | AHB_CLK_FROM_DDR |
272 CPU_AND_DDR_CLK_FROM_DDR | CPU_AND_DDR_CLK_FROM_CPU |
273 CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV |
274 CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) |
275 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) |
276 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1), pll_regs + QCA956X_PLL_CLK_CTRL_REG);
277
278 /* ddr_pll_dither_unset */
279 writel(DDR_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_DDR_DIT_FRAC_REG);
280 writel(DDR_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_DDR_DIT2_FRAC_REG);
281
282 /* cpu_pll_dither_unset */
283 writel(CPU_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_CPU_DIT_FRAC_REG);
284 writel(CPU_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_CPU_DIT2_FRAC_REG);
285
286 /* pll_pwd_unset */
287 cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(0));
288 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0));
289
290 /* outdiv_unset */
291 cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL2);
292 ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL2);
293
294 /* pll_bypass_unset */
295 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
296 CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
297 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
298 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
299 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
300 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
301
302 while (readl(pll_regs + QCA956X_PLL_CPU_CONFIG_REG) & 0x8000000)
303 /* NOP */;
304
305 while (readl(pll_regs + QCA956X_PLL_DDR_CONFIG_REG) & 0x8000000)
306 /* NOP */;
307 }
308
get_clocks(void)309 int get_clocks(void)
310 {
311 void __iomem *regs;
312 u32 ref_rate, cpu_rate, ddr_rate, ahb_rate;
313 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl;
314 u32 pll, cpu_pll, ddr_pll, misc;
315
316 /*
317 * QCA956x timer init workaround has to be applied right before setting
318 * up the clock. Else, there will be no jiffies
319 */
320 regs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
321 MAP_NOCACHE);
322 misc = readl(regs + AR71XX_RESET_REG_MISC_INT_ENABLE);
323 misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
324 writel(misc, regs + AR71XX_RESET_REG_MISC_INT_ENABLE);
325
326 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
327 MAP_NOCACHE);
328 pll = readl(regs + QCA956X_PLL_CPU_CONFIG_REG);
329 out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
330 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
331 ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
332 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
333
334 pll = readl(regs + QCA956X_PLL_CPU_CONFIG1_REG);
335 nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
336 QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
337 hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
338 QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
339 lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
340 QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
341
342 ref_rate = qca956x_get_xtal();
343
344 cpu_pll = nint * ref_rate / ref_div;
345 cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
346 cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
347 cpu_pll /= (1 << out_div);
348
349 pll = readl(regs + QCA956X_PLL_DDR_CONFIG_REG);
350 out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
351 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
352 ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
353 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
354 pll = readl(regs + QCA956X_PLL_DDR_CONFIG1_REG);
355 nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
356 QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
357 hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
358 QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
359 lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
360 QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
361
362 ddr_pll = nint * ref_rate / ref_div;
363 ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
364 ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
365 ddr_pll /= (1 << out_div);
366
367 clk_ctrl = readl(regs + QCA956X_PLL_CLK_CTRL_REG);
368
369 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
370 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
371
372 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
373 cpu_rate = ref_rate;
374 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
375 cpu_rate = ddr_pll / (postdiv + 1);
376 else
377 cpu_rate = cpu_pll / (postdiv + 1);
378
379 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
380 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
381
382 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
383 ddr_rate = ref_rate;
384 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
385 ddr_rate = cpu_pll / (postdiv + 1);
386 else
387 ddr_rate = ddr_pll / (postdiv + 1);
388
389 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
390 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
391
392 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
393 ahb_rate = ref_rate;
394 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
395 ahb_rate = ddr_pll / (postdiv + 1);
396 else
397 ahb_rate = cpu_pll / (postdiv + 1);
398
399 gd->cpu_clk = cpu_rate;
400 gd->mem_clk = ddr_rate;
401 gd->bus_clk = ahb_rate;
402
403 debug("cpu_clk=%u, ddr_clk=%u, bus_clk=%u\n",
404 cpu_rate, ddr_rate, ahb_rate);
405
406 return 0;
407 }
408
get_bus_freq(ulong dummy)409 ulong get_bus_freq(ulong dummy)
410 {
411 if (!gd->bus_clk)
412 get_clocks();
413 return gd->bus_clk;
414 }
415
get_ddr_freq(ulong dummy)416 ulong get_ddr_freq(ulong dummy)
417 {
418 if (!gd->mem_clk)
419 get_clocks();
420 return gd->mem_clk;
421 }
422