1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
4 */
5
6/ {
7	aliases {
8		gpio0 = &gpioa;
9		gpio1 = &gpiob;
10		gpio2 = &gpioc;
11		gpio3 = &gpiod;
12		gpio4 = &gpioe;
13		gpio5 = &gpiof;
14		gpio6 = &gpiog;
15		gpio7 = &gpioh;
16		gpio8 = &gpioi;
17		pinctrl0 = &pinctrl;
18	};
19
20#if defined(CONFIG_TFABOOT)
21	firmware {
22		optee {
23			bootph-all;
24		};
25	};
26
27	/* need PSCI for sysreset during board_f */
28	psci {
29		bootph-some-ram;
30	};
31#else
32	binman: binman {
33		multiple-images;
34
35		spl-stm32 {
36			filename = "u-boot-spl.stm32";
37			mkimage {
38				args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000";
39				u-boot-spl {
40					no-write-symbols;
41				};
42			};
43		};
44	};
45
46	clocks {
47		bootph-all;
48
49		clk_hse: ck_hse {
50			bootph-all;
51			#clock-cells = <0>;
52			compatible = "fixed-clock";
53			clock-frequency = <24000000>;
54		};
55
56		clk_hsi: ck_hsi {
57			bootph-all;
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <64000000>;
61		};
62
63		clk_lse: ck_lse {
64			bootph-all;
65			#clock-cells = <0>;
66			compatible = "fixed-clock";
67			clock-frequency = <32768>;
68		};
69
70		clk_lsi: ck_lsi {
71			bootph-all;
72			#clock-cells = <0>;
73			compatible = "fixed-clock";
74			clock-frequency = <32000>;
75		};
76
77		clk_csi: ck_csi {
78			bootph-all;
79			#clock-cells = <0>;
80			compatible = "fixed-clock";
81			clock-frequency = <4000000>;
82		};
83	};
84
85	cpu0_opp_table: cpu0-opp-table {
86		compatible = "operating-points-v2";
87		opp-shared;
88		bootph-pre-ram;
89		opp-650000000 {
90			bootph-pre-ram;
91			opp-hz = /bits/ 64 <650000000>;
92			opp-microvolt = <1200000>;
93			opp-supported-hw = <0x1>;
94		};
95		opp-1000000000 {
96			bootph-pre-ram;
97			opp-hz = /bits/ 64 <1000000000>;
98			opp-microvolt = <1350000>;
99			opp-supported-hw = <0x2>;
100		};
101	};
102
103	reboot {
104		bootph-all;
105		compatible = "syscon-reboot";
106		regmap = <&rcc>;
107		offset = <0x114>;
108		mask = <0x1>;
109	};
110#endif
111
112	soc {
113		bootph-all;
114
115		ddr: ddr@5a003000 {
116			bootph-all;
117
118			compatible = "st,stm32mp13-ddr";
119
120			reg = <0x5A003000 0x550
121			       0x5A004000 0x234>;
122
123			status = "okay";
124		};
125	};
126};
127
128&bsec {
129	bootph-all;
130};
131
132&etzpc {
133	bootph-all;
134};
135
136#if !defined(CONFIG_TFABOOT)
137&cpu0 {
138	nvmem-cells = <&part_number_otp>;
139	nvmem-cell-names = "part_number";
140	operating-points-v2 = <&cpu0_opp_table>;
141};
142#endif
143
144&gpioa {
145	bootph-all;
146};
147
148&gpiob {
149	bootph-all;
150};
151
152&gpioc {
153	bootph-all;
154};
155
156&gpiod {
157	bootph-all;
158};
159
160&gpioe {
161	bootph-all;
162};
163
164&gpiof {
165	bootph-all;
166};
167
168&gpiog {
169	bootph-all;
170};
171
172&gpioh {
173	bootph-all;
174};
175
176&gpioi {
177	bootph-all;
178};
179
180&iwdg2 {
181	bootph-all;
182};
183
184&pinctrl {
185	bootph-all;
186};
187
188&rcc {
189	bootph-all;
190};
191
192&scmi {
193	bootph-all;
194};
195
196&scmi_clk {
197	bootph-all;
198};
199
200&scmi_reset {
201	bootph-all;
202};
203
204&syscfg {
205	bootph-all;
206};
207
208&usbphyc {
209	/* stm32-usbphyc-clk = ck_usbo_48m is a source clock of RCC CCF */
210	bootph-all;
211};
212