1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 SiFive, Inc
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * Limitations:
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
13 */
14
15 #include <clk.h>
16 #include <div64.h>
17 #include <dm.h>
18 #include <pwm.h>
19 #include <regmap.h>
20 #include <asm/global_data.h>
21 #include <linux/io.h>
22 #include <linux/log2.h>
23 #include <linux/bitfield.h>
24
25 /* PWMCFG fields */
26 #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
27 #define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
28 #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
29 #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
30 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
31 #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
32 #define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
33 #define PWM_SIFIVE_PWMCFG_GANG BIT(24)
34 #define PWM_SIFIVE_PWMCFG_IP BIT(28)
35
36 /* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
37 #define PWM_SIFIVE_SIZE_PWMCMP 4
38 #define PWM_SIFIVE_CMPWIDTH 16
39
40 #define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0
41 #define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 struct pwm_sifive_regs {
46 unsigned long cfg;
47 unsigned long cnt;
48 unsigned long pwms;
49 unsigned long cmp0;
50 };
51
52 struct pwm_sifive_data {
53 struct pwm_sifive_regs regs;
54 };
55
56 struct pwm_sifive_priv {
57 void __iomem *base;
58 ulong freq;
59 const struct pwm_sifive_data *data;
60 };
61
pwm_sifive_set_config(struct udevice * dev,uint channel,uint period_ns,uint duty_ns)62 static int pwm_sifive_set_config(struct udevice *dev, uint channel,
63 uint period_ns, uint duty_ns)
64 {
65 struct pwm_sifive_priv *priv = dev_get_priv(dev);
66 const struct pwm_sifive_regs *regs = &priv->data->regs;
67 unsigned long scale_pow;
68 unsigned long long num;
69 u32 scale, val = 0, frac;
70
71 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
72
73 /*
74 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
75 * period length is using pwmscale which provides the number of bits the
76 * counter is shifted before being feed to the comparators. A period
77 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
78 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
79 */
80 scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000);
81 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
82 val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS);
83
84 /*
85 * The problem of output producing mixed setting as mentioned at top,
86 * occurs here. To minimize the window for this problem, we are
87 * calculating the register values first and then writing them
88 * consecutively
89 */
90 num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
91 frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
92 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
93 frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
94
95 writel(val, priv->base + regs->cfg);
96 writel(frac, priv->base + regs->cmp0 + channel *
97 PWM_SIFIVE_SIZE_PWMCMP);
98
99 return 0;
100 }
101
pwm_sifive_set_enable(struct udevice * dev,uint channel,bool enable)102 static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable)
103 {
104 struct pwm_sifive_priv *priv = dev_get_priv(dev);
105 const struct pwm_sifive_regs *regs = &priv->data->regs;
106
107 debug("%s: Enable '%s'\n", __func__, dev->name);
108
109 if (enable)
110 writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
111 regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
112 else
113 writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
114 regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
115
116 return 0;
117 }
118
pwm_sifive_of_to_plat(struct udevice * dev)119 static int pwm_sifive_of_to_plat(struct udevice *dev)
120 {
121 struct pwm_sifive_priv *priv = dev_get_priv(dev);
122
123 priv->base = dev_read_addr_ptr(dev);
124
125 return 0;
126 }
127
pwm_sifive_probe(struct udevice * dev)128 static int pwm_sifive_probe(struct udevice *dev)
129 {
130 struct pwm_sifive_priv *priv = dev_get_priv(dev);
131 struct clk clk;
132 int ret = 0;
133
134 ret = clk_get_by_index(dev, 0, &clk);
135 if (ret < 0) {
136 debug("%s get clock fail!\n", __func__);
137 return -EINVAL;
138 }
139
140 priv->freq = clk_get_rate(&clk);
141 priv->data = (struct pwm_sifive_data *)dev_get_driver_data(dev);
142
143 return 0;
144 }
145
146 static const struct pwm_ops pwm_sifive_ops = {
147 .set_config = pwm_sifive_set_config,
148 .set_enable = pwm_sifive_set_enable,
149 };
150
151 static const struct pwm_sifive_data pwm_data = {
152 .regs = {
153 .cfg = 0x00,
154 .cnt = 0x08,
155 .pwms = 0x10,
156 .cmp0 = 0x20,
157 },
158 };
159
160 static const struct udevice_id pwm_sifive_ids[] = {
161 { .compatible = "sifive,pwm0", .data = (ulong)&pwm_data},
162 { }
163 };
164
165 U_BOOT_DRIVER(pwm_sifive) = {
166 .name = "pwm_sifive",
167 .id = UCLASS_PWM,
168 .of_match = pwm_sifive_ids,
169 .ops = &pwm_sifive_ops,
170 .of_to_plat = pwm_sifive_of_to_plat,
171 .probe = pwm_sifive_probe,
172 .priv_auto = sizeof(struct pwm_sifive_priv),
173 };
174