1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <dm.h>
7 #include <init.h>
8 #include <dm/device-internal.h>
9 #include <pci.h>
10 #include <asm/io.h>
11 #include <asm/irq.h>
12 #include <asm/post.h>
13 #include <asm/arch/device.h>
14 #include <asm/arch/tnc.h>
15 #include <asm/fsp1/fsp_support.h>
16 #include <asm/processor.h>
17
disable_igd(void)18 static int __maybe_unused disable_igd(void)
19 {
20 struct udevice *igd = NULL;
21 struct udevice *sdvo = NULL;
22 int ret;
23
24 /*
25 * In case the IGD and SDVO devices were already in disabled state,
26 * we should return and not proceed any further.
27 */
28 dm_pci_bus_find_bdf(TNC_IGD, &igd);
29 dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
30 if (!igd || !sdvo)
31 return 0;
32
33 /*
34 * According to Atom E6xx datasheet, setting VGA Disable (bit17)
35 * of Graphics Controller register (offset 0x50) prevents IGD
36 * (D2:F0) from reporting itself as a VGA display controller
37 * class in the PCI configuration space, and should also prevent
38 * it from responding to VGA legacy memory range and I/O addresses.
39 *
40 * However test result shows that with just VGA Disable bit set and
41 * a PCIe graphics card connected to one of the PCIe controllers on
42 * the E6xx, accessing the VGA legacy space still causes system hang.
43 * After a number of attempts, it turns out besides VGA Disable bit,
44 * the SDVO (D3:F0) device should be disabled to make it work.
45 *
46 * To simplify, use the Function Disable register (offset 0xc4)
47 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
48 * two devices will be completely disabled (invisible in the PCI
49 * configuration space) unless a system reset is performed.
50 */
51 dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
52 dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
53
54 /*
55 * After setting the function disable bit, IGD and SDVO devices will
56 * disappear in the PCI configuration space. This however creates an
57 * inconsistent state from a driver model PCI controller point of view,
58 * as these two PCI devices are still attached to its parent's child
59 * device list as maintained by the driver model. Some driver model PCI
60 * APIs like dm_pci_find_class(), are referring to the list to speed up
61 * the finding process instead of re-enumerating the whole PCI bus, so
62 * it gets the stale cached data which is wrong.
63 *
64 * Note x86 PCI enueration normally happens twice, in pre-relocation
65 * phase and post-relocation. One option might be to call disable_igd()
66 * in one of the pre-relocation initialization hooks so that it gets
67 * disabled in the first round, and when it comes to the second round
68 * driver model PCI will construct a correct list. Unfortunately this
69 * does not work as Intel FSP is used on this platform to perform low
70 * level initialization, and fsp_init_phase_pci() is called only once
71 * in the post-relocation phase. If we disable IGD and SDVO devices,
72 * fsp_init_phase_pci() simply hangs and never returns.
73 *
74 * So the only option we have is to manually remove these two devices.
75 */
76 ret = device_remove(igd, DM_REMOVE_NORMAL);
77 if (ret)
78 return ret;
79 ret = device_unbind(igd);
80 if (ret)
81 return ret;
82 ret = device_remove(sdvo, DM_REMOVE_NORMAL);
83 if (ret)
84 return ret;
85 ret = device_unbind(sdvo);
86 if (ret)
87 return ret;
88
89 return 0;
90 }
91
arch_cpu_init(void)92 int arch_cpu_init(void)
93 {
94 post_code(POST_CPU_INIT);
95
96 return x86_cpu_init_f();
97 }
98
tnc_irq_init(void)99 static void tnc_irq_init(void)
100 {
101 struct tnc_rcba *rcba;
102 u32 base;
103
104 pci_read_config32(TNC_LPC, LPC_RCBA, &base);
105 base &= ~MEM_BAR_EN;
106 rcba = (struct tnc_rcba *)base;
107
108 /* Make sure all internal PCI devices are using INTA */
109 writel(INTA, &rcba->d02ip);
110 writel(INTA, &rcba->d03ip);
111 writel(INTA, &rcba->d27ip);
112 writel(INTA, &rcba->d31ip);
113 writel(INTA, &rcba->d23ip);
114 writel(INTA, &rcba->d24ip);
115 writel(INTA, &rcba->d25ip);
116 writel(INTA, &rcba->d26ip);
117
118 /*
119 * Route TunnelCreek PCI device interrupt pin to PIRQ
120 *
121 * Since PCIe downstream ports received INTx are routed to PIRQ
122 * A/B/C/D directly and not configurable, we have to route PCIe
123 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
124 * on TunneCreek, route them to PIRQ E/F/G/H.
125 */
126 writew(PIRQE, &rcba->d02ir);
127 writew(PIRQF, &rcba->d03ir);
128 writew(PIRQG, &rcba->d27ir);
129 writew(PIRQH, &rcba->d31ir);
130 writew(PIRQA, &rcba->d23ir);
131 writew(PIRQB, &rcba->d24ir);
132 writew(PIRQC, &rcba->d25ir);
133 writew(PIRQD, &rcba->d26ir);
134 }
135
arch_early_init_r(void)136 int arch_early_init_r(void)
137 {
138 int ret = 0;
139
140 #ifdef CONFIG_DISABLE_IGD
141 ret = disable_igd();
142 #endif
143
144 tnc_irq_init();
145
146 return ret;
147 }
148