1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Xilinx Zynq 7000 DTSI 4 * Describes the hardware common to all Zynq 7000-based boards. 5 * 6 * Copyright (C) 2011 - 2015 Xilinx 7 */ 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 compatible = "xlnx,zynq-7000"; 13 14 options { 15 u-boot { 16 compatible = "u-boot,config"; 17 bootscr-address = /bits/ 64 <0x3000000>; 18 }; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "arm,cortex-a9"; 27 device_type = "cpu"; 28 reg = <0>; 29 clocks = <&clkc 3>; 30 clock-latency = <1000>; 31 cpu0-supply = <®ulator_vccpint>; 32 operating-points = < 33 /* kHz uV */ 34 666667 1000000 35 333334 1000000 36 >; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "arm,cortex-a9"; 41 device_type = "cpu"; 42 reg = <1>; 43 clocks = <&clkc 3>; 44 }; 45 }; 46 47 fpga_full: fpga-region { 48 compatible = "fpga-region"; 49 fpga-mgr = <&devcfg>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 ranges; 53 }; 54 55 pmu@f8891000 { 56 compatible = "arm,cortex-a9-pmu"; 57 interrupts = <0 5 4>, <0 6 4>; 58 interrupt-parent = <&intc>; 59 reg = <0xf8891000 0x1000>, 60 <0xf8893000 0x1000>; 61 }; 62 63 regulator_vccpint: fixedregulator { 64 compatible = "regulator-fixed"; 65 regulator-name = "VCCPINT"; 66 regulator-min-microvolt = <1000000>; 67 regulator-max-microvolt = <1000000>; 68 regulator-boot-on; 69 regulator-always-on; 70 }; 71 72 replicator { 73 compatible = "arm,coresight-static-replicator"; 74 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 75 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 76 77 out-ports { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 /* replicator output ports */ 82 port@0 { 83 reg = <0>; 84 replicator_out_port0: endpoint { 85 remote-endpoint = <&tpiu_in_port>; 86 }; 87 }; 88 port@1 { 89 reg = <1>; 90 replicator_out_port1: endpoint { 91 remote-endpoint = <&etb_in_port>; 92 }; 93 }; 94 }; 95 in-ports { 96 /* replicator input port */ 97 port { 98 replicator_in_port0: endpoint { 99 remote-endpoint = <&funnel_out_port>; 100 }; 101 }; 102 }; 103 }; 104 105 amba: axi { 106 bootph-all; 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 interrupt-parent = <&intc>; 111 ranges; 112 113 adc: adc@f8007100 { 114 compatible = "xlnx,zynq-xadc-1.00.a"; 115 reg = <0xf8007100 0x20>; 116 interrupts = <0 7 4>; 117 interrupt-parent = <&intc>; 118 clocks = <&clkc 12>; 119 }; 120 121 can0: can@e0008000 { 122 compatible = "xlnx,zynq-can-1.0"; 123 status = "disabled"; 124 clocks = <&clkc 19>, <&clkc 36>; 125 clock-names = "can_clk", "pclk"; 126 reg = <0xe0008000 0x1000>; 127 interrupts = <0 28 4>; 128 interrupt-parent = <&intc>; 129 tx-fifo-depth = <0x40>; 130 rx-fifo-depth = <0x40>; 131 }; 132 133 can1: can@e0009000 { 134 compatible = "xlnx,zynq-can-1.0"; 135 status = "disabled"; 136 clocks = <&clkc 20>, <&clkc 37>; 137 clock-names = "can_clk", "pclk"; 138 reg = <0xe0009000 0x1000>; 139 interrupts = <0 51 4>; 140 interrupt-parent = <&intc>; 141 tx-fifo-depth = <0x40>; 142 rx-fifo-depth = <0x40>; 143 }; 144 145 gpio0: gpio@e000a000 { 146 compatible = "xlnx,zynq-gpio-1.0"; 147 #gpio-cells = <2>; 148 clocks = <&clkc 42>; 149 gpio-controller; 150 interrupt-controller; 151 #interrupt-cells = <2>; 152 interrupt-parent = <&intc>; 153 interrupts = <0 20 4>; 154 reg = <0xe000a000 0x1000>; 155 }; 156 157 i2c0: i2c@e0004000 { 158 compatible = "cdns,i2c-r1p10"; 159 status = "disabled"; 160 clocks = <&clkc 38>; 161 interrupt-parent = <&intc>; 162 interrupts = <0 25 4>; 163 clock-frequency = <400000>; 164 reg = <0xe0004000 0x1000>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 }; 168 169 i2c1: i2c@e0005000 { 170 compatible = "cdns,i2c-r1p10"; 171 status = "disabled"; 172 clocks = <&clkc 39>; 173 interrupt-parent = <&intc>; 174 interrupts = <0 48 4>; 175 clock-frequency = <400000>; 176 reg = <0xe0005000 0x1000>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 }; 180 181 intc: interrupt-controller@f8f01000 { 182 compatible = "arm,cortex-a9-gic"; 183 #interrupt-cells = <3>; 184 interrupt-controller; 185 reg = <0xF8F01000 0x1000>, 186 <0xF8F00100 0x100>; 187 }; 188 189 L2: cache-controller@f8f02000 { 190 compatible = "arm,pl310-cache"; 191 reg = <0xF8F02000 0x1000>; 192 interrupts = <0 2 4>; 193 arm,data-latency = <3 2 2>; 194 arm,tag-latency = <2 2 2>; 195 cache-unified; 196 cache-level = <2>; 197 }; 198 199 mc: memory-controller@f8006000 { 200 compatible = "xlnx,zynq-ddrc-a05"; 201 reg = <0xf8006000 0x1000>; 202 }; 203 204 ocm: sram@fffc0000 { 205 compatible = "mmio-sram"; 206 reg = <0xfffc0000 0x10000>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges = <0 0xfffc0000 0x10000>; 210 ocm-sram@0 { 211 reg = <0x0 0x10000>; 212 }; 213 }; 214 215 uart0: serial@e0000000 { 216 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 217 status = "disabled"; 218 clocks = <&clkc 23>, <&clkc 40>; 219 clock-names = "uart_clk", "pclk"; 220 reg = <0xE0000000 0x1000>; 221 interrupts = <0 27 4>; 222 }; 223 224 uart1: serial@e0001000 { 225 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 226 status = "disabled"; 227 clocks = <&clkc 24>, <&clkc 41>; 228 clock-names = "uart_clk", "pclk"; 229 reg = <0xE0001000 0x1000>; 230 interrupts = <0 50 4>; 231 }; 232 233 spi0: spi@e0006000 { 234 compatible = "xlnx,zynq-spi-r1p6"; 235 reg = <0xe0006000 0x1000>; 236 status = "disabled"; 237 interrupt-parent = <&intc>; 238 interrupts = <0 26 4>; 239 clocks = <&clkc 25>, <&clkc 34>; 240 clock-names = "ref_clk", "pclk"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 }; 244 245 spi1: spi@e0007000 { 246 compatible = "xlnx,zynq-spi-r1p6"; 247 reg = <0xe0007000 0x1000>; 248 status = "disabled"; 249 interrupt-parent = <&intc>; 250 interrupts = <0 49 4>; 251 clocks = <&clkc 26>, <&clkc 35>; 252 clock-names = "ref_clk", "pclk"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 }; 256 257 qspi: spi@e000d000 { 258 compatible = "xlnx,zynq-qspi-1.0"; 259 reg = <0xe000d000 0x1000>; 260 interrupt-parent = <&intc>; 261 interrupts = <0 19 4>; 262 clocks = <&clkc 10>, <&clkc 43>; 263 clock-names = "ref_clk", "pclk"; 264 status = "disabled"; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 gem0: ethernet@e000b000 { 270 compatible = "xlnx,zynq-gem", "cdns,gem"; 271 reg = <0xe000b000 0x1000>; 272 status = "disabled"; 273 interrupts = <0 22 4>; 274 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 275 clock-names = "pclk", "hclk", "tx_clk"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 }; 279 280 gem1: ethernet@e000c000 { 281 compatible = "xlnx,zynq-gem", "cdns,gem"; 282 reg = <0xe000c000 0x1000>; 283 status = "disabled"; 284 interrupts = <0 45 4>; 285 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 286 clock-names = "pclk", "hclk", "tx_clk"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 }; 290 291 smcc: memory-controller@e000e000 { 292 compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 293 reg = <0xe000e000 0x0001000>; 294 status = "disabled"; 295 clock-names = "memclk", "apb_pclk"; 296 clocks = <&clkc 11>, <&clkc 44>; 297 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 298 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 299 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 300 #address-cells = <2>; 301 #size-cells = <1>; 302 interrupt-parent = <&intc>; 303 interrupts = <0 18 4>; 304 305 nfc0: nand-controller@0,0 { 306 compatible = "arm,pl353-nand-r2p1"; 307 reg = <0 0 0x1000000>; 308 status = "disabled"; 309 }; 310 nor0: flash@1,0 { 311 status = "disabled"; 312 compatible = "cfi-flash"; 313 reg = <1 0 0x2000000>; 314 }; 315 }; 316 317 sdhci0: mmc@e0100000 { 318 compatible = "arasan,sdhci-8.9a"; 319 status = "disabled"; 320 clock-names = "clk_xin", "clk_ahb"; 321 clocks = <&clkc 21>, <&clkc 32>; 322 interrupt-parent = <&intc>; 323 interrupts = <0 24 4>; 324 reg = <0xe0100000 0x1000>; 325 }; 326 327 sdhci1: mmc@e0101000 { 328 compatible = "arasan,sdhci-8.9a"; 329 status = "disabled"; 330 clock-names = "clk_xin", "clk_ahb"; 331 clocks = <&clkc 22>, <&clkc 33>; 332 interrupt-parent = <&intc>; 333 interrupts = <0 47 4>; 334 reg = <0xe0101000 0x1000>; 335 }; 336 337 slcr: slcr@f8000000 { 338 bootph-all; 339 #address-cells = <1>; 340 #size-cells = <1>; 341 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 342 reg = <0xF8000000 0x1000>; 343 ranges; 344 clkc: clkc@100 { 345 bootph-all; 346 #clock-cells = <1>; 347 compatible = "xlnx,ps7-clkc"; 348 fclk-enable = <0xf>; 349 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 350 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 351 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 352 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 353 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 354 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 355 "gem1_aper", "sdio0_aper", "sdio1_aper", 356 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 357 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 358 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 359 "dbg_trc", "dbg_apb"; 360 reg = <0x100 0x100>; 361 }; 362 363 rstc: rstc@200 { 364 compatible = "xlnx,zynq-reset"; 365 reg = <0x200 0x48>; 366 #reset-cells = <1>; 367 syscon = <&slcr>; 368 }; 369 370 pinctrl0: pinctrl@700 { 371 compatible = "xlnx,pinctrl-zynq"; 372 reg = <0x700 0x200>; 373 syscon = <&slcr>; 374 }; 375 }; 376 377 dmac_s: dma-controller@f8003000 { 378 compatible = "arm,pl330", "arm,primecell"; 379 reg = <0xf8003000 0x1000>; 380 interrupt-parent = <&intc>; 381 /* 382 * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 383 * "dma4", "dma5", "dma6", "dma7"; 384 */ 385 interrupts = <0 13 4>, 386 <0 14 4>, <0 15 4>, 387 <0 16 4>, <0 17 4>, 388 <0 40 4>, <0 41 4>, 389 <0 42 4>, <0 43 4>; 390 #dma-cells = <1>; 391 clocks = <&clkc 27>; 392 clock-names = "apb_pclk"; 393 }; 394 395 devcfg: devcfg@f8007000 { 396 compatible = "xlnx,zynq-devcfg-1.0"; 397 reg = <0xf8007000 0x100>; 398 interrupt-parent = <&intc>; 399 interrupts = <0 8 4>; 400 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 401 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 402 syscon = <&slcr>; 403 }; 404 405 efuse: efuse@f800d000 { 406 compatible = "xlnx,zynq-efuse"; 407 reg = <0xf800d000 0x20>; 408 }; 409 410 global_timer: timer@f8f00200 { 411 compatible = "arm,cortex-a9-global-timer"; 412 reg = <0xf8f00200 0x20>; 413 interrupts = <1 11 0x301>; 414 interrupt-parent = <&intc>; 415 clocks = <&clkc 4>; 416 }; 417 418 ttc0: timer@f8001000 { 419 interrupt-parent = <&intc>; 420 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 421 compatible = "cdns,ttc"; 422 clocks = <&clkc 6>; 423 reg = <0xF8001000 0x1000>; 424 }; 425 426 ttc1: timer@f8002000 { 427 interrupt-parent = <&intc>; 428 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 429 compatible = "cdns,ttc"; 430 clocks = <&clkc 6>; 431 reg = <0xF8002000 0x1000>; 432 }; 433 434 scutimer: timer@f8f00600 { 435 bootph-all; 436 interrupt-parent = <&intc>; 437 interrupts = <1 13 0x301>; 438 compatible = "arm,cortex-a9-twd-timer"; 439 reg = <0xf8f00600 0x20>; 440 clocks = <&clkc 4>; 441 }; 442 443 usb0: usb@e0002000 { 444 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 445 status = "disabled"; 446 clocks = <&clkc 28>; 447 interrupt-parent = <&intc>; 448 interrupts = <0 21 4>; 449 reg = <0xe0002000 0x1000>; 450 phy_type = "ulpi"; 451 }; 452 453 usb1: usb@e0003000 { 454 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 455 status = "disabled"; 456 clocks = <&clkc 29>; 457 interrupt-parent = <&intc>; 458 interrupts = <0 44 4>; 459 reg = <0xe0003000 0x1000>; 460 phy_type = "ulpi"; 461 }; 462 463 watchdog0: watchdog@f8005000 { 464 clocks = <&clkc 45>; 465 compatible = "cdns,wdt-r1p2"; 466 interrupt-parent = <&intc>; 467 interrupts = <0 9 1>; 468 reg = <0xf8005000 0x1000>; 469 timeout-sec = <10>; 470 }; 471 472 etb@f8801000 { 473 compatible = "arm,coresight-etb10", "arm,primecell"; 474 reg = <0xf8801000 0x1000>; 475 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 476 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 477 in-ports { 478 port { 479 etb_in_port: endpoint { 480 remote-endpoint = <&replicator_out_port1>; 481 }; 482 }; 483 }; 484 }; 485 486 tpiu@f8803000 { 487 compatible = "arm,coresight-tpiu", "arm,primecell"; 488 reg = <0xf8803000 0x1000>; 489 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 490 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 491 in-ports { 492 port { 493 tpiu_in_port: endpoint { 494 remote-endpoint = <&replicator_out_port0>; 495 }; 496 }; 497 }; 498 }; 499 500 funnel@f8804000 { 501 compatible = "arm,coresight-static-funnel", "arm,primecell"; 502 reg = <0xf8804000 0x1000>; 503 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 504 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 505 506 /* funnel output ports */ 507 out-ports { 508 port { 509 funnel_out_port: endpoint { 510 remote-endpoint = 511 <&replicator_in_port0>; 512 }; 513 }; 514 }; 515 516 in-ports { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 520 /* funnel input ports */ 521 port@0 { 522 reg = <0>; 523 funnel0_in_port0: endpoint { 524 remote-endpoint = <&ptm0_out_port>; 525 }; 526 }; 527 528 port@1 { 529 reg = <1>; 530 funnel0_in_port1: endpoint { 531 remote-endpoint = <&ptm1_out_port>; 532 }; 533 }; 534 535 port@2 { 536 reg = <2>; 537 funnel0_in_port2: endpoint { 538 }; 539 }; 540 /* The other input ports are not connect to anything */ 541 }; 542 }; 543 544 ptm@f889c000 { 545 compatible = "arm,coresight-etm3x", "arm,primecell"; 546 reg = <0xf889c000 0x1000>; 547 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 548 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 549 cpu = <&cpu0>; 550 out-ports { 551 port { 552 ptm0_out_port: endpoint { 553 remote-endpoint = <&funnel0_in_port0>; 554 }; 555 }; 556 }; 557 }; 558 559 ptm@f889d000 { 560 compatible = "arm,coresight-etm3x", "arm,primecell"; 561 reg = <0xf889d000 0x1000>; 562 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 563 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 564 cpu = <&cpu1>; 565 out-ports { 566 port { 567 ptm1_out_port: endpoint { 568 remote-endpoint = <&funnel0_in_port1>; 569 }; 570 }; 571 }; 572 }; 573 }; 574}; 575