1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5 #include <command.h>
6 #include <dm.h>
7 #include <env.h>
8 #include <clk.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <asm/armv7.h>
12 #include <asm/global_data.h>
13 #include <asm/arch-rockchip/bootrom.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cpu_rk3288.h>
16 #include <asm/arch-rockchip/cru.h>
17 #include <asm/arch-rockchip/hardware.h>
18 #include <asm/arch-rockchip/grf_rk3288.h>
19 #include <asm/arch-rockchip/pmu_rk3288.h>
20 #include <asm/arch-rockchip/qos_rk3288.h>
21 #include <asm/arch-rockchip/sdram.h>
22 #include <linux/err.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define GRF_BASE 0xff770000
27
28 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
29 [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
30 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff130000/flash@0",
31 [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
32 };
33
34 #ifdef CONFIG_XPL_BUILD
configure_l2ctlr(void)35 static void configure_l2ctlr(void)
36 {
37 u32 l2ctlr;
38
39 l2ctlr = read_l2ctlr();
40 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
41
42 /*
43 * Data RAM write latency: 2 cycles
44 * Data RAM read latency: 2 cycles
45 * Data RAM setup latency: 1 cycle
46 * Tag RAM write latency: 1 cycle
47 * Tag RAM read latency: 1 cycle
48 * Tag RAM setup latency: 1 cycle
49 */
50 l2ctlr |= (1 << 3 | 1 << 0);
51 write_l2ctlr(l2ctlr);
52 }
53 #endif
54
rk3288_qos_init(void)55 int rk3288_qos_init(void)
56 {
57 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
58 /* set vop qos to higher priority */
59 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
60 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
61
62 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
63 "rockchip,rk3288-tinker")) {
64 /* set isp qos to higher priority */
65 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
68 }
69
70 return 0;
71 }
72
arch_cpu_init(void)73 int arch_cpu_init(void)
74 {
75 #ifdef CONFIG_XPL_BUILD
76 configure_l2ctlr();
77 #else
78 /* We do some SoC one time setting here. */
79 struct rk3288_grf * const grf = (void *)GRF_BASE;
80
81 /* Use rkpwm by default */
82 rk_setreg(&grf->soc_con2, 1 << 0);
83
84 /*
85 * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
86 * cleared
87 */
88 rk_clrreg(&grf->soc_con0, 1 << 12);
89
90 rk3288_qos_init();
91 #endif
92
93 return 0;
94 }
95
96 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)97 void board_debug_uart_init(void)
98 {
99 /* Enable early UART on the RK3288 */
100 struct rk3288_grf * const grf = (void *)GRF_BASE;
101
102 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
103 GPIO7C6_MASK << GPIO7C6_SHIFT,
104 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
105 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
106 }
107 #endif
108
rk3288_board_late_init(void)109 __weak int rk3288_board_late_init(void)
110 {
111 return 0;
112 }
113
rk_board_late_init(void)114 int rk_board_late_init(void)
115 {
116 return rk3288_board_late_init();
117 }
118
ft_rk3288w_setup(void * blob)119 static int ft_rk3288w_setup(void *blob)
120 {
121 const char *path;
122 int offs, ret;
123
124 path = "/clock-controller@ff760000";
125 offs = fdt_path_offset(blob, path);
126 if (offs < 0) {
127 debug("failed to found fdt path %s\n", path);
128 return offs;
129 }
130
131 ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru");
132 if (ret) {
133 printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret);
134 return ret;
135 }
136
137 return ret;
138 }
139
ft_system_setup(void * blob,struct bd_info * bd)140 int ft_system_setup(void *blob, struct bd_info *bd)
141 {
142 if (soc_is_rk3288w())
143 return ft_rk3288w_setup(blob);
144
145 return 0;
146 }
147
do_clock(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])148 static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
149 char *const argv[])
150 {
151 static const struct {
152 char *name;
153 int id;
154 } clks[] = {
155 { "osc", CLK_OSC },
156 { "apll", CLK_ARM },
157 { "dpll", CLK_DDR },
158 { "cpll", CLK_CODEC },
159 { "gpll", CLK_GENERAL },
160 #ifdef CONFIG_ROCKCHIP_RK3036
161 { "mpll", CLK_NEW },
162 #else
163 { "npll", CLK_NEW },
164 #endif
165 };
166 int ret, i;
167 struct udevice *dev;
168
169 ret = rockchip_get_clk(&dev);
170 if (ret) {
171 printf("clk-uclass not found\n");
172 return 0;
173 }
174
175 for (i = 0; i < ARRAY_SIZE(clks); i++) {
176 struct clk clk;
177 ulong rate;
178
179 clk.id = clks[i].id;
180 ret = clk_request(dev, &clk);
181 if (ret < 0)
182 continue;
183
184 rate = clk_get_rate(&clk);
185 printf("%s: %lu\n", clks[i].name, rate);
186 }
187
188 return 0;
189 }
190
191 U_BOOT_CMD(
192 clock, 2, 1, do_clock,
193 "display information about clocks",
194 ""
195 );
196