1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <command.h>
7 #include <cpu.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <dm/lists.h>
11 #include <event.h>
12 #include <hang.h>
13 #include <init.h>
14 #include <irq_func.h>
15 #include <log.h>
16 #include <asm/encoding.h>
17 #include <asm/system.h>
18 #include <asm/hwcap.h>
19 #include <asm/cpufeature.h>
20 #include <asm/cache.h>
21 #include <asm/global_data.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/bitops.h>
24 #include <linux/log2.h>
25 #include <linux/ctype.h>
26
27 /*
28 * The variables here must be stored in the data section since they are used
29 * before the bss section is available.
30 */
31 #if !CONFIG_IS_ENABLED(XIP)
32 u32 hart_lottery __section(".data") = 0;
33
34 #ifdef CONFIG_AVAILABLE_HARTS
35 /*
36 * The main hart running U-Boot has acquired available_harts_lock until it has
37 * finished initialization of global data.
38 */
39 u32 available_harts_lock = 1;
40 #endif
41 #endif
42
43 /* Host ISA bitmap */
44 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __section(".data");
45
46 static unsigned int riscv_cbom_block_size __section(".data");
47 static unsigned int riscv_cboz_block_size __section(".data");
48 /**
49 * __riscv_isa_extension_available() - Check whether given extension
50 * is available or not
51 *
52 * @bit: bit position of the desired extension
53 * Return: true or false
54 *
55 */
__riscv_isa_extension_available(unsigned int bit)56 static bool __riscv_isa_extension_available(unsigned int bit)
57 {
58 if (bit >= RISCV_ISA_EXT_MAX)
59 return false;
60
61 return test_bit(bit, riscv_isa) ? true : false;
62 }
63
riscv_get_cbom_block_size(void)64 inline unsigned int riscv_get_cbom_block_size(void)
65 {
66 return riscv_cbom_block_size;
67 }
68
riscv_get_cboz_block_size(void)69 inline unsigned int riscv_get_cboz_block_size(void)
70 {
71 return riscv_cboz_block_size;
72 }
73
riscv_ext_zicbom_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)74 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
75 const unsigned long *isa_bitmap)
76 {
77 struct udevice *dev;
78
79 if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || riscv_cbom_block_size)
80 return 0;
81
82 uclass_first_device(UCLASS_CPU, &dev);
83 if (!dev) {
84 log_info("Failed to get cpu device!\n");
85 return -ENXIO;
86 }
87
88 if (!dev_read_u32(dev, "riscv,cbom-block-size",
89 &riscv_cbom_block_size)) {
90 if (!riscv_cbom_block_size) {
91 log_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
92 return -EINVAL;
93 }
94 if (!is_power_of_2(riscv_cbom_block_size)) {
95 log_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
96 return -EINVAL;
97 }
98 return 0;
99 } else {
100 return -EINVAL;
101 }
102 }
103
riscv_ext_zicboz_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)104 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
105 const unsigned long *isa_bitmap)
106 {
107 struct udevice *dev;
108
109 if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || riscv_cboz_block_size)
110 return 0;
111
112 uclass_first_device(UCLASS_CPU, &dev);
113 if (!dev) {
114 log_debug("Failed to get cpu device!\n");
115 return -ENXIO;
116 }
117
118 if (!dev_read_u32(dev, "riscv,cboz-block-size",
119 &riscv_cboz_block_size)) {
120 if (!riscv_cboz_block_size) {
121 log_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
122 return -EINVAL;
123 }
124 if (!is_power_of_2(riscv_cboz_block_size)) {
125 log_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
126 return -EINVAL;
127 }
128 return 0;
129 } else {
130 return -EINVAL;
131 }
132 }
133
riscv_ext_zca_depends(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)134 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
135 const unsigned long *isa_bitmap)
136 {
137 if (__riscv_isa_extension_available(RISCV_ISA_EXT_ZCA))
138 return 0;
139
140 return -EINVAL;
141 }
142
riscv_ext_zcd_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)143 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
144 const unsigned long *isa_bitmap)
145 {
146 if (__riscv_isa_extension_available(RISCV_ISA_EXT_ZCA) &&
147 __riscv_isa_extension_available(RISCV_ISA_EXT_d))
148 return 0;
149
150 return -EINVAL;
151 }
152
riscv_ext_zcf_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)153 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
154 const unsigned long *isa_bitmap)
155 {
156 if (IS_ENABLED(CONFIG_64BIT))
157 return -EINVAL;
158
159 if (__riscv_isa_extension_available(RISCV_ISA_EXT_ZCA) &&
160 __riscv_isa_extension_available(RISCV_ISA_EXT_f))
161 return 0;
162
163 return -EINVAL;
164 }
165
166 static const unsigned int riscv_zk_bundled_exts[] = {
167 RISCV_ISA_EXT_ZBKB,
168 RISCV_ISA_EXT_ZBKC,
169 RISCV_ISA_EXT_ZBKX,
170 RISCV_ISA_EXT_ZKND,
171 RISCV_ISA_EXT_ZKNE,
172 RISCV_ISA_EXT_ZKR,
173 RISCV_ISA_EXT_ZKT,
174 };
175
176 static const unsigned int riscv_zkn_bundled_exts[] = {
177 RISCV_ISA_EXT_ZBKB,
178 RISCV_ISA_EXT_ZBKC,
179 RISCV_ISA_EXT_ZBKX,
180 RISCV_ISA_EXT_ZKND,
181 RISCV_ISA_EXT_ZKNE,
182 RISCV_ISA_EXT_ZKNH,
183 };
184
185 static const unsigned int riscv_zks_bundled_exts[] = {
186 RISCV_ISA_EXT_ZBKB,
187 RISCV_ISA_EXT_ZBKC,
188 RISCV_ISA_EXT_ZKSED,
189 RISCV_ISA_EXT_ZKSH
190 };
191
192 #define RISCV_ISA_EXT_ZVKN \
193 RISCV_ISA_EXT_ZVKNED, \
194 RISCV_ISA_EXT_ZVKNHB, \
195 RISCV_ISA_EXT_ZVKB, \
196 RISCV_ISA_EXT_ZVKT
197
198 static const unsigned int riscv_zvkn_bundled_exts[] = {
199 RISCV_ISA_EXT_ZVKN
200 };
201
202 static const unsigned int riscv_zvknc_bundled_exts[] = {
203 RISCV_ISA_EXT_ZVKN,
204 RISCV_ISA_EXT_ZVBC
205 };
206
207 static const unsigned int riscv_zvkng_bundled_exts[] = {
208 RISCV_ISA_EXT_ZVKN,
209 RISCV_ISA_EXT_ZVKG
210 };
211
212 #define RISCV_ISA_EXT_ZVKS \
213 RISCV_ISA_EXT_ZVKSED, \
214 RISCV_ISA_EXT_ZVKSH, \
215 RISCV_ISA_EXT_ZVKB, \
216 RISCV_ISA_EXT_ZVKT
217
218 static const unsigned int riscv_zvks_bundled_exts[] = {
219 RISCV_ISA_EXT_ZVKS
220 };
221
222 static const unsigned int riscv_zvksc_bundled_exts[] = {
223 RISCV_ISA_EXT_ZVKS,
224 RISCV_ISA_EXT_ZVBC
225 };
226
227 static const unsigned int riscv_zvksg_bundled_exts[] = {
228 RISCV_ISA_EXT_ZVKS,
229 RISCV_ISA_EXT_ZVKG
230 };
231
232 static const unsigned int riscv_zvbb_exts[] = {
233 RISCV_ISA_EXT_ZVKB
234 };
235
236 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \
237 RISCV_ISA_EXT_ZVE64X, \
238 RISCV_ISA_EXT_ZVE32F, \
239 RISCV_ISA_EXT_ZVE32X
240
241 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \
242 RISCV_ISA_EXT_ZVE64F, \
243 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
244
245 #define RISCV_ISA_EXT_V_IMPLY_LIST \
246 RISCV_ISA_EXT_ZVE64D, \
247 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
248
249 static const unsigned int riscv_zve32f_exts[] = {
250 RISCV_ISA_EXT_ZVE32X
251 };
252
253 static const unsigned int riscv_zve64f_exts[] = {
254 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
255 };
256
257 static const unsigned int riscv_zve64d_exts[] = {
258 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
259 };
260
261 static const unsigned int riscv_v_exts[] = {
262 RISCV_ISA_EXT_V_IMPLY_LIST
263 };
264
265 static const unsigned int riscv_zve64x_exts[] = {
266 RISCV_ISA_EXT_ZVE32X,
267 RISCV_ISA_EXT_ZVE64X
268 };
269
270 /*
271 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
272 * privileged ISA, the existence of the CSRs is implied by any extension which
273 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
274 * existence of the CSR, and treat it as a subset of those other extensions.
275 */
276 static const unsigned int riscv_xlinuxenvcfg_exts[] = {
277 RISCV_ISA_EXT_XLINUXENVCFG
278 };
279
280 /*
281 * Zc* spec states that:
282 * - C always implies Zca
283 * - C+F implies Zcf (RV32 only)
284 * - C+D implies Zcd
285 *
286 * These extensions will be enabled and then validated depending on the
287 * availability of F/D RV32.
288 */
289 static const unsigned int riscv_c_exts[] = {
290 RISCV_ISA_EXT_ZCA,
291 RISCV_ISA_EXT_ZCF,
292 RISCV_ISA_EXT_ZCD,
293 };
294
295 /*
296 * The canonical order of ISA extension names in the ISA string is defined in
297 * chapter 27 of the unprivileged specification.
298 *
299 * Ordinarily, for in-kernel data structures, this order is unimportant but
300 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
301 *
302 * The specification uses vague wording, such as should, when it comes to
303 * ordering, so for our purposes the following rules apply:
304 *
305 * 1. All multi-letter extensions must be separated from other extensions by an
306 * underscore.
307 *
308 * 2. Additional standard extensions (starting with 'Z') must be sorted after
309 * single-letter extensions and before any higher-privileged extensions.
310 *
311 * 3. The first letter following the 'Z' conventionally indicates the most
312 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
313 * If multiple 'Z' extensions are named, they must be ordered first by
314 * category, then alphabetically within a category.
315 *
316 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
317 * after standard unprivileged extensions. If multiple supervisor-level
318 * extensions are listed, they must be ordered alphabetically.
319 *
320 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
321 * after any lower-privileged, standard extensions. If multiple
322 * machine-level extensions are listed, they must be ordered
323 * alphabetically.
324 *
325 * 5. Non-standard extensions (starting with 'X') must be listed after all
326 * standard extensions. If multiple non-standard extensions are listed, they
327 * must be ordered alphabetically.
328 *
329 * An example string following the order is:
330 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
331 *
332 * New entries to this struct should follow the ordering rules described above.
333 */
334 const struct riscv_isa_ext_data riscv_isa_ext[] = {
335 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
336 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
337 __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
338 __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
339 __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
340 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
341 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
342 __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
343 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
344 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts,
345 riscv_ext_zicbom_validate),
346 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts,
347 riscv_ext_zicboz_validate),
348 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
349 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
350 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
351 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
352 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
353 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
354 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
355 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
356 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
357 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
358 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
359 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
360 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
361 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
362 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
363 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
364 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
365 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
366 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
367 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
368 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
369 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
370 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
371 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
372 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
373 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
374 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
375 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
376 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
377 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
378 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
379 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
380 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
381 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
382 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
383 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
384 __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
385 __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
386 __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
387 __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
388 __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
389 __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
390 __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
391 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
392 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
393 __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
394 __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
395 __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
396 __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
397 __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
398 __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
399 __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
400 __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
401 __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
402 __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
403 __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
404 __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
405 __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
406 __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
407 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
408 __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
409 __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
410 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
411 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
412 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
413 __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
414 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
415 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
416 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
417 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
418 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
419 };
420
421 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
422
riscv_isa_set_ext(const struct riscv_isa_ext_data * ext,unsigned long * bitmap)423 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap)
424 {
425 if (ext->id != RISCV_ISA_EXT_INVALID)
426 __set_bit(ext->id, bitmap);
427
428 for (int i = 0; i < ext->subset_ext_size; i++) {
429 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)
430 __set_bit(ext->subset_ext_ids[i], bitmap);
431 }
432 }
433
match_isa_ext(const char * name,const char * name_end)434 static void match_isa_ext(const char *name, const char *name_end)
435 {
436 for (int i = 0; i < riscv_isa_ext_count; i++) {
437 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
438
439 if ((name_end - name == strlen(ext->name)) &&
440 !strncasecmp(name, ext->name, name_end - name)) {
441 if (ext->validate && !ext->validate(ext, riscv_isa))
442 riscv_isa_set_ext(ext, riscv_isa);
443 break;
444 }
445 }
446 }
447
riscv_parse_isa_string(const char * isa)448 static void riscv_parse_isa_string(const char *isa)
449 {
450 /*
451 * For all possible cpus, we have already validated in
452 * the boot process that they at least contain "rv" and
453 * whichever of "32"/"64" this kernel supports, and so this
454 * section can be skipped.
455 */
456 isa += 4;
457
458 while (*isa) {
459 const char *ext = isa++;
460 const char *ext_end = isa;
461 bool ext_err = false;
462
463 switch (*ext) {
464 case 'x':
465 case 'X':
466 log_warning("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
467 /*
468 * To skip an extension, we find its end.
469 * As multi-letter extensions must be split from other multi-letter
470 * extensions with an "_", the end of a multi-letter extension will
471 * either be the null character or the "_" at the start of the next
472 * multi-letter extension.
473 */
474 for (; *isa && *isa != '_'; ++isa)
475 ;
476 ext_err = true;
477 break;
478 case 's':
479 /*
480 * Workaround for invalid single-letter 's' & 'u' (QEMU).
481 * No need to set the bit in riscv_isa as 's' & 'u' are
482 * not valid ISA extensions. It works unless the first
483 * multi-letter extension in the ISA string begins with
484 * "Su" and is not prefixed with an underscore.
485 */
486 if (ext[-1] != '_' && ext[1] == 'u') {
487 ++isa;
488 ext_err = true;
489 break;
490 }
491 fallthrough;
492 case 'S':
493 case 'z':
494 case 'Z':
495 /*
496 * Before attempting to parse the extension itself, we find its end.
497 * As multi-letter extensions must be split from other multi-letter
498 * extensions with an "_", the end of a multi-letter extension will
499 * either be the null character or the "_" at the start of the next
500 * multi-letter extension.
501 *
502 * Next, as the extensions version is currently ignored, we
503 * eliminate that portion. This is done by parsing backwards from
504 * the end of the extension, removing any numbers. This may be a
505 * major or minor number however, so the process is repeated if a
506 * minor number was found.
507 *
508 * ext_end is intended to represent the first character *after* the
509 * name portion of an extension, but will be decremented to the last
510 * character itself while eliminating the extensions version number.
511 * A simple re-increment solves this problem.
512 */
513 for (; *isa && *isa != '_'; ++isa)
514 if (unlikely(!isalnum(*isa)))
515 ext_err = true;
516
517 ext_end = isa;
518 if (unlikely(ext_err))
519 break;
520
521 if (!isdigit(ext_end[-1]))
522 break;
523
524 while (isdigit(*--ext_end))
525 ;
526
527 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
528 ++ext_end;
529 break;
530 }
531
532 while (isdigit(*--ext_end))
533 ;
534
535 ++ext_end;
536 break;
537 default:
538 /*
539 * Things are a little easier for single-letter extensions, as they
540 * are parsed forwards.
541 *
542 * After checking that our starting position is valid, we need to
543 * ensure that, when isa was incremented at the start of the loop,
544 * that it arrived at the start of the next extension.
545 *
546 * If we are already on a non-digit, there is nothing to do. Either
547 * we have a multi-letter extension's _, or the start of an
548 * extension.
549 *
550 * Otherwise we have found the current extension's major version
551 * number. Parse past it, and a subsequent p/minor version number
552 * if present. The `p` extension must not appear immediately after
553 * a number, so there is no fear of missing it.
554 *
555 */
556 if (unlikely(!isalpha(*ext))) {
557 ext_err = true;
558 break;
559 }
560
561 if (!isdigit(*isa))
562 break;
563
564 while (isdigit(*++isa))
565 ;
566
567 if (tolower(*isa) != 'p')
568 break;
569
570 if (!isdigit(*++isa)) {
571 --isa;
572 break;
573 }
574
575 while (isdigit(*++isa))
576 ;
577
578 break;
579 }
580
581 /*
582 * The parser expects that at the start of an iteration isa points to the
583 * first character of the next extension. As we stop parsing an extension
584 * on meeting a non-alphanumeric character, an extra increment is needed
585 * where the succeeding extension is a multi-letter prefixed with an "_".
586 */
587 if (*isa == '_')
588 ++isa;
589
590 if (unlikely(ext_err))
591 continue;
592 match_isa_ext(ext, ext_end);
593 }
594 }
595
supports_extension(char ext)596 static inline bool supports_extension(char ext)
597 {
598 #if CONFIG_IS_ENABLED(RISCV_MMODE)
599 return csr_read(CSR_MISA) & (1 << (ext - 'a'));
600 #elif CONFIG_CPU
601 return __riscv_isa_extension_available(ext);
602 #else /* !CONFIG_CPU */
603 #warning "There is no way to determine the available extensions in S-mode."
604 #warning "Please convert your board to use the RISC-V CPU driver."
605 return false;
606 #endif /* CONFIG_CPU */
607 }
608
riscv_cpu_probe(void)609 static int riscv_cpu_probe(void)
610 {
611 if (CONFIG_IS_ENABLED(CPU)) {
612 int ret;
613
614 /* probe cpus so that RISC-V timer can be bound */
615 ret = cpu_probe_all();
616 if (ret)
617 return log_msg_ret("RISC-V cpus probe failed\n", ret);
618 }
619
620 return 0;
621 }
622 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, riscv_cpu_probe);
623
624 /*
625 * This is called on secondary harts just after the IPI is init'd. Currently
626 * there's nothing to do, since we just need to clear any existing IPIs, and
627 * that is handled by the sending of an ipi itself.
628 */
629 #if CONFIG_IS_ENABLED(SMP)
dummy_pending_ipi_clear(ulong hart,ulong arg0,ulong arg1)630 static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
631 {
632 }
633 #endif
634
riscv_cpu_setup(void)635 int riscv_cpu_setup(void)
636 {
637 int ret = -ENODEV, ext_count, i;
638 const char *isa, **exts;
639 struct udevice *dev;
640
641 uclass_find_first_device(UCLASS_CPU, &dev);
642 if (!dev) {
643 debug("unable to find the RISC-V cpu device\n");
644 return ret;
645 }
646
647 ext_count = dev_read_string_list(dev, "riscv,isa-extensions", &exts);
648 if (ext_count > 0) {
649 for (i = 0; i < ext_count; i++)
650 match_isa_ext(exts[i], exts[i] + strlen(exts[i]));
651 } else {
652 isa = dev_read_string(dev, "riscv,isa");
653 if (!isa)
654 return ret;
655 riscv_parse_isa_string(isa);
656 }
657
658 /* Enable FPU */
659 if (supports_extension('d') || supports_extension('f')) {
660 csr_set(MODE_PREFIX(status), MSTATUS_FS);
661 csr_write(CSR_FCSR, 0);
662 }
663
664 if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
665 /*
666 * Enable perf counters for cycle, time,
667 * and instret counters only
668 */
669 if (supports_extension('u')) {
670 #ifdef CONFIG_RISCV_PRIV_1_9
671 csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
672 csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
673 #else
674 csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
675 #endif
676 }
677
678 /* Disable paging */
679 if (supports_extension('s'))
680 #ifdef CONFIG_RISCV_PRIV_1_9
681 csr_read_clear(CSR_MSTATUS, SR_VM);
682 #else
683 csr_write(CSR_SATP, 0);
684 #endif
685 }
686
687 #if CONFIG_IS_ENABLED(SMP)
688 ret = riscv_init_ipi();
689 if (ret)
690 return ret;
691
692 /*
693 * Clear all pending IPIs on secondary harts. We don't do anything on
694 * the boot hart, since we never send an IPI to ourselves, and no
695 * interrupts are enabled
696 */
697 ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
698 if (ret)
699 return ret;
700 #endif
701
702 return 0;
703 }
704 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
705
arch_early_init_r(void)706 int arch_early_init_r(void)
707 {
708 if (IS_ENABLED(CONFIG_SYSRESET_SBI))
709 device_bind_driver(gd->dm_root, "sbi-sysreset",
710 "sbi-sysreset", NULL);
711
712 return 0;
713 }
714
715 /**
716 * harts_early_init() - A callback function called by start.S to configure
717 * feature settings of each hart.
718 *
719 * In a multi-core system, memory access shall be careful here, it shall
720 * take care of race conditions.
721 */
harts_early_init(void)722 __weak void harts_early_init(void)
723 {
724 }
725
726 #if !CONFIG_IS_ENABLED(SYSRESET)
reset_cpu(void)727 void reset_cpu(void)
728 {
729 printf("resetting ...\n");
730
731 printf("reset not supported yet\n");
732 hang();
733 }
734 #endif
735
736 /*
737 * cleanup_before_linux() is called just before we call linux, which prepares
738 * the processor for linux.
739 * this weak implementation is used by default. we disable interrupts and flush
740 * the cache.
741 */
cleanup_before_linux(void)742 __weak int cleanup_before_linux(void)
743 {
744 disable_interrupts();
745
746 cache_flush();
747
748 return 0;
749 }
750
arch_setup_gd(gd_t * new_gd)751 void arch_setup_gd(gd_t *new_gd)
752 {
753 set_gd(new_gd);
754 }
755