1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell MMC/SD/SDIO driver
4 *
5 * (C) Copyright 2012-2014
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Maen Suleiman, Gerald Kerma
8 */
9
10 #include <errno.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <dm.h>
14 #include <fdtdec.h>
15 #include <part.h>
16 #include <mmc.h>
17 #include <asm/io.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <mvebu_mmc.h>
21 #include <dm/device_compat.h>
22
23 #define MVEBU_TARGET_DRAM 0
24
25 #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
26
get_regbase(const struct mmc * mmc)27 static inline void *get_regbase(const struct mmc *mmc)
28 {
29 struct mvebu_mmc_plat *pdata = mmc->priv;
30
31 return pdata->iobase;
32 }
33
mvebu_mmc_write(const struct mmc * mmc,u32 offs,u32 val)34 static void mvebu_mmc_write(const struct mmc *mmc, u32 offs, u32 val)
35 {
36 writel(val, get_regbase(mmc) + (offs));
37 }
38
mvebu_mmc_read(const struct mmc * mmc,u32 offs)39 static u32 mvebu_mmc_read(const struct mmc *mmc, u32 offs)
40 {
41 return readl(get_regbase(mmc) + (offs));
42 }
43
mvebu_mmc_setup_data(struct udevice * dev,struct mmc_data * data)44 static int mvebu_mmc_setup_data(struct udevice *dev, struct mmc_data *data)
45 {
46 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
47 struct mmc *mmc = &pdata->mmc;
48 u32 ctrl_reg;
49
50 dev_dbg(dev, "data %s : blocks=%d blksz=%d\n",
51 (data->flags & MMC_DATA_READ) ? "read" : "write",
52 data->blocks, data->blocksize);
53
54 /* default to maximum timeout */
55 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
56 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
57 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
58
59 if (data->flags & MMC_DATA_READ) {
60 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
61 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
62 } else {
63 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
64 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
65 }
66
67 mvebu_mmc_write(mmc, SDIO_BLK_COUNT, data->blocks);
68 mvebu_mmc_write(mmc, SDIO_BLK_SIZE, data->blocksize);
69
70 return 0;
71 }
72
mvebu_mmc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)73 static int mvebu_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
74 struct mmc_data *data)
75 {
76 ulong start;
77 ushort waittype = 0;
78 ushort resptype = 0;
79 ushort xfertype = 0;
80 ushort resp_indx = 0;
81 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
82 struct mmc *mmc = &pdata->mmc;
83
84 dev_dbg(dev, "cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
85 cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
86
87 dev_dbg(dev, "cmd %d (hw state 0x%04x)\n",
88 cmd->cmdidx, mvebu_mmc_read(mmc, SDIO_HW_STATE));
89
90 /*
91 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
92 * register is sometimes not set before a while when some
93 * "unusual" data block sizes are used (such as with the SWITCH
94 * command), even despite the fact that the XFER_DONE interrupt
95 * was raised. And if another data transfer starts before
96 * this bit comes to good sense (which eventually happens by
97 * itself) then the new transfer simply fails with a timeout.
98 */
99 if (!(mvebu_mmc_read(mmc, SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
100 ushort hw_state, count = 0;
101
102 start = get_timer(0);
103 do {
104 hw_state = mvebu_mmc_read(mmc, SDIO_HW_STATE);
105 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
106 printf("%s : FIFO_EMPTY bit missing\n",
107 dev->name);
108 break;
109 }
110 count++;
111 } while (!(hw_state & CMD_FIFO_EMPTY));
112 dev_dbg(dev, "*** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
113 hw_state, count, (get_timer(0) - (start)));
114 }
115
116 /* Clear status */
117 mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
118 mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
119
120 resptype = SDIO_CMD_INDEX(cmd->cmdidx);
121
122 /* Analyzing resptype/xfertype/waittype for the command */
123 if (cmd->resp_type & MMC_RSP_BUSY)
124 resptype |= SDIO_CMD_RSP_48BUSY;
125 else if (cmd->resp_type & MMC_RSP_136)
126 resptype |= SDIO_CMD_RSP_136;
127 else if (cmd->resp_type & MMC_RSP_PRESENT)
128 resptype |= SDIO_CMD_RSP_48;
129 else
130 resptype |= SDIO_CMD_RSP_NONE;
131
132 if (cmd->resp_type & MMC_RSP_CRC)
133 resptype |= SDIO_CMD_CHECK_CMDCRC;
134
135 if (cmd->resp_type & MMC_RSP_OPCODE)
136 resptype |= SDIO_CMD_INDX_CHECK;
137
138 if (cmd->resp_type & MMC_RSP_PRESENT) {
139 resptype |= SDIO_UNEXPECTED_RESP;
140 waittype |= SDIO_NOR_UNEXP_RSP;
141 }
142
143 if (data) {
144 int err = mvebu_mmc_setup_data(dev, data);
145
146 if (err) {
147 dev_dbg(dev, "command DATA error :%x\n", err);
148 return err;
149 }
150
151 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
152 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
153 if (data->flags & MMC_DATA_READ) {
154 xfertype |= SDIO_XFER_MODE_TO_HOST;
155 waittype = SDIO_NOR_DMA_INI;
156 } else {
157 waittype |= SDIO_NOR_XFER_DONE;
158 }
159 } else {
160 waittype |= SDIO_NOR_CMD_DONE;
161 }
162
163 /* Setting cmd arguments */
164 mvebu_mmc_write(mmc, SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
165 mvebu_mmc_write(mmc, SDIO_ARG_HI, cmd->cmdarg >> 16);
166
167 /* Setting Xfer mode */
168 mvebu_mmc_write(mmc, SDIO_XFER_MODE, xfertype);
169
170 /* Sending command */
171 mvebu_mmc_write(mmc, SDIO_CMD, resptype);
172
173 start = get_timer(0);
174
175 while (!((mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS)) & waittype)) {
176 if (mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
177 dev_dbg(dev, "error! cmdidx : %d, err reg: %04x\n",
178 cmd->cmdidx,
179 mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS));
180 if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
181 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
182 dev_dbg(dev, "command READ timed out\n");
183 return -ETIMEDOUT;
184 }
185 dev_dbg(dev, "command READ error\n");
186 return -ECOMM;
187 }
188
189 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
190 dev_dbg(dev, "command timed out\n");
191 return -ETIMEDOUT;
192 }
193 }
194
195 /* Handling response */
196 if (cmd->resp_type & MMC_RSP_136) {
197 uint response[8];
198
199 for (resp_indx = 0; resp_indx < 8; resp_indx++)
200 response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
201
202 cmd->response[0] = ((response[0] & 0x03ff) << 22) |
203 ((response[1] & 0xffff) << 6) |
204 ((response[2] & 0xfc00) >> 10);
205 cmd->response[1] = ((response[2] & 0x03ff) << 22) |
206 ((response[3] & 0xffff) << 6) |
207 ((response[4] & 0xfc00) >> 10);
208 cmd->response[2] = ((response[4] & 0x03ff) << 22) |
209 ((response[5] & 0xffff) << 6) |
210 ((response[6] & 0xfc00) >> 10);
211 cmd->response[3] = ((response[6] & 0x03ff) << 22) |
212 ((response[7] & 0x3fff) << 8);
213 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
214 uint response[3];
215
216 for (resp_indx = 0; resp_indx < 3; resp_indx++)
217 response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
218
219 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
220 ((response[1] & 0xffff) << (14 - 8)) |
221 ((response[0] & 0x03ff) << (30 - 8));
222 cmd->response[1] = ((response[0] & 0xfc00) >> 10);
223 cmd->response[2] = 0;
224 cmd->response[3] = 0;
225 } else {
226 cmd->response[0] = 0;
227 cmd->response[1] = 0;
228 cmd->response[2] = 0;
229 cmd->response[3] = 0;
230 }
231
232 dev_dbg(dev, "resp[0x%x] ", cmd->resp_type);
233 debug("[0x%x] ", cmd->response[0]);
234 debug("[0x%x] ", cmd->response[1]);
235 debug("[0x%x] ", cmd->response[2]);
236 debug("[0x%x] ", cmd->response[3]);
237 debug("\n");
238
239 if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
240 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
241 return -ETIMEDOUT;
242
243 return 0;
244 }
245
mvebu_mmc_power_up(struct udevice * dev)246 static void mvebu_mmc_power_up(struct udevice *dev)
247 {
248 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
249 struct mmc *mmc = &pdata->mmc;
250
251 dev_dbg(dev, "power up\n");
252
253 /* disable interrupts */
254 mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
255 mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
256
257 /* SW reset */
258 mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
259
260 mvebu_mmc_write(mmc, SDIO_XFER_MODE, 0);
261
262 /* enable status */
263 mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
264 mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
265
266 /* enable interrupts status */
267 mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
268 mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
269 }
270
mvebu_mmc_set_clk(struct udevice * dev,unsigned int clock)271 static void mvebu_mmc_set_clk(struct udevice *dev, unsigned int clock)
272 {
273 unsigned int m;
274 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
275 struct mmc *mmc = &pdata->mmc;
276
277 if (clock == 0) {
278 dev_dbg(dev, "clock off\n");
279 mvebu_mmc_write(mmc, SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
280 mvebu_mmc_write(mmc, SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
281 } else {
282 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
283 if (m > MVEBU_MMC_BASE_DIV_MAX)
284 m = MVEBU_MMC_BASE_DIV_MAX;
285 mvebu_mmc_write(mmc, SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
286 dev_dbg(dev, "clock (%d) div : %d\n", clock, m);
287 }
288 }
289
mvebu_mmc_set_bus(struct udevice * dev,unsigned int bus)290 static void mvebu_mmc_set_bus(struct udevice *dev, unsigned int bus)
291 {
292 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
293 struct mmc *mmc = &pdata->mmc;
294 u32 ctrl_reg = 0;
295
296 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
297 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
298
299 switch (bus) {
300 case 4:
301 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
302 break;
303 case 1:
304 default:
305 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
306 }
307
308 /* default transfer mode */
309 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
310 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
311
312 /* default to maximum timeout */
313 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
314 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
315
316 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
317
318 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
319
320 dev_dbg(dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
321 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
322 "push-pull" : "open-drain",
323 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
324 "4bit-width" : "1bit-width",
325 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
326 "high-speed" : "");
327
328 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
329 }
330
mvebu_mmc_set_ios(struct udevice * dev)331 static int mvebu_mmc_set_ios(struct udevice *dev)
332 {
333 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
334 struct mmc *mmc = &pdata->mmc;
335
336 dev_dbg(dev, "bus[%d] clock[%d]\n",
337 mmc->bus_width, mmc->clock);
338 mvebu_mmc_set_bus(dev, mmc->bus_width);
339 mvebu_mmc_set_clk(dev, mmc->clock);
340
341 return 0;
342 }
343
344 /*
345 * Set window register.
346 */
mvebu_window_setup(const struct mmc * mmc)347 static void mvebu_window_setup(const struct mmc *mmc)
348 {
349 int i;
350
351 for (i = 0; i < 4; i++) {
352 mvebu_mmc_write(mmc, WINDOW_CTRL(i), 0);
353 mvebu_mmc_write(mmc, WINDOW_BASE(i), 0);
354 }
355 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
356 u32 size, base, attrib;
357
358 /* Enable DRAM bank */
359 switch (i) {
360 case 0:
361 attrib = KWCPU_ATTR_DRAM_CS0;
362 break;
363 case 1:
364 attrib = KWCPU_ATTR_DRAM_CS1;
365 break;
366 case 2:
367 attrib = KWCPU_ATTR_DRAM_CS2;
368 break;
369 case 3:
370 attrib = KWCPU_ATTR_DRAM_CS3;
371 break;
372 default:
373 /* invalide bank, disable access */
374 attrib = 0;
375 break;
376 }
377
378 size = gd->bd->bi_dram[i].size;
379 base = gd->bd->bi_dram[i].start;
380 if (size && attrib) {
381 mvebu_mmc_write(mmc, WINDOW_CTRL(i),
382 MVCPU_WIN_CTRL_DATA(size,
383 MVEBU_TARGET_DRAM,
384 attrib,
385 MVCPU_WIN_ENABLE));
386 } else {
387 mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
388 }
389 mvebu_mmc_write(mmc, WINDOW_BASE(i), base);
390 }
391 }
392
mvebu_mmc_initialize(struct udevice * dev)393 static int mvebu_mmc_initialize(struct udevice *dev)
394 {
395 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
396 struct mmc *mmc = &pdata->mmc;
397
398 dev_dbg(dev, "%s\n", __func__);
399
400 /*
401 * Setting host parameters
402 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
403 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
404 */
405 mvebu_mmc_write(mmc, SDIO_HOST_CTRL,
406 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
407 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
408 SDIO_HOST_CTRL_BIG_ENDIAN |
409 SDIO_HOST_CTRL_PUSH_PULL_EN |
410 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
411
412 mvebu_mmc_write(mmc, SDIO_CLK_CTRL, 0);
413
414 /* enable status */
415 mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
416 mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
417
418 /* disable interrupts */
419 mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
420 mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
421
422 mvebu_window_setup(mmc);
423
424 /* SW reset */
425 mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
426
427 return 0;
428 }
429
mvebu_mmc_of_to_plat(struct udevice * dev)430 static int mvebu_mmc_of_to_plat(struct udevice *dev)
431 {
432 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
433 fdt_addr_t addr;
434
435 addr = dev_read_addr(dev);
436 if (addr == FDT_ADDR_T_NONE)
437 return -EINVAL;
438
439 pdata->iobase = (void *)addr;
440
441 return 0;
442 }
443
mvebu_mmc_probe(struct udevice * dev)444 static int mvebu_mmc_probe(struct udevice *dev)
445 {
446 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
447 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
448 struct mmc *mmc = &pdata->mmc;
449 struct mmc_config *cfg = &pdata->cfg;
450
451 cfg->name = dev->name;
452 cfg->f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX;
453 cfg->f_max = MVEBU_MMC_CLOCKRATE_MAX;
454 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
455 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
456 cfg->part_type = PART_TYPE_DOS;
457 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
458
459 mmc->cfg = cfg;
460 mmc->priv = pdata;
461 mmc->dev = dev;
462 upriv->mmc = mmc;
463
464 mvebu_mmc_power_up(dev);
465 mvebu_mmc_initialize(dev);
466
467 return 0;
468 }
469
470 static const struct dm_mmc_ops mvebu_dm_mmc_ops = {
471 .send_cmd = mvebu_mmc_send_cmd,
472 .set_ios = mvebu_mmc_set_ios,
473 };
474
mvebu_mmc_bind(struct udevice * dev)475 static int mvebu_mmc_bind(struct udevice *dev)
476 {
477 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
478
479 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
480 }
481
482 static const struct udevice_id mvebu_mmc_match[] = {
483 { .compatible = "marvell,orion-sdio" },
484 { /* sentinel */ }
485 };
486
487 U_BOOT_DRIVER(mvebu_mmc) = {
488 .name = "mvebu_mmc",
489 .id = UCLASS_MMC,
490 .of_match = mvebu_mmc_match,
491 .ops = &mvebu_dm_mmc_ops,
492 .probe = mvebu_mmc_probe,
493 .bind = mvebu_mmc_bind,
494 .of_to_plat = mvebu_mmc_of_to_plat,
495 .plat_auto = sizeof(struct mvebu_mmc_plat),
496 };
497