1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVIDIA Tegra SPI-SLINK controller
4 *
5 * Copyright (c) 2010-2013 NVIDIA Corporation
6 */
7
8 #include <dm.h>
9 #include <log.h>
10 #include <time.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <spi.h>
16 #include <fdtdec.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include "tegra_spi.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 /* COMMAND */
24 #define SLINK_CMD_ENB BIT(31)
25 #define SLINK_CMD_GO BIT(30)
26 #define SLINK_CMD_M_S BIT(28)
27 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
28 #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
29 #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
30 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
31 #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
32 #define SLINK_CMD_CS_POL3 BIT(23)
33 #define SLINK_CMD_CS_POL2 BIT(22)
34 #define SLINK_CMD_CK_SDA BIT(21)
35 #define SLINK_CMD_CS_POL1 BIT(20)
36 #define SLINK_CMD_CS_POL BIT(13)
37 #define SLINK_CMD_CS_VAL BIT(12)
38 #define SLINK_CMD_CS_SOFT BIT(11)
39 #define SLINK_CMD_BIT_LENGTH BIT(4)
40 #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
41 /* COMMAND2 */
42 #define SLINK_CMD2_TXEN BIT(30)
43 #define SLINK_CMD2_RXEN BIT(31)
44 #define SLINK_CMD2_SS_EN BIT(18)
45 #define SLINK_CMD2_SS_EN_SHIFT 18
46 #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
47 #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
48 /* STATUS */
49 #define SLINK_STAT_BSY BIT(31)
50 #define SLINK_STAT_RDY BIT(30)
51 #define SLINK_STAT_ERR BIT(29)
52 #define SLINK_STAT_RXF_FLUSH BIT(27)
53 #define SLINK_STAT_TXF_FLUSH BIT(26)
54 #define SLINK_STAT_RXF_OVF BIT(25)
55 #define SLINK_STAT_TXF_UNR BIT(24)
56 #define SLINK_STAT_RXF_EMPTY BIT(23)
57 #define SLINK_STAT_RXF_FULL BIT(22)
58 #define SLINK_STAT_TXF_EMPTY BIT(21)
59 #define SLINK_STAT_TXF_FULL BIT(20)
60 #define SLINK_STAT_TXF_OVF BIT(19)
61 #define SLINK_STAT_RXF_UNR BIT(18)
62 #define SLINK_STAT_CUR_BLKCNT BIT(15)
63 /* STATUS2 */
64 #define SLINK_STAT2_RXF_FULL_CNT BIT(16)
65 #define SLINK_STAT2_TXF_FULL_CNT BIT(0)
66
67 #define SPI_TIMEOUT 1000
68 #define TEGRA_SPI_MAX_FREQ 52000000
69
70 unsigned int cmd_cs_pol_bit[] = {
71 SLINK_CMD_CS_POL,
72 SLINK_CMD_CS_POL1,
73 SLINK_CMD_CS_POL2,
74 SLINK_CMD_CS_POL3,
75 };
76
77 struct spi_regs {
78 u32 command; /* SLINK_COMMAND_0 register */
79 u32 command2; /* SLINK_COMMAND2_0 reg */
80 u32 status; /* SLINK_STATUS_0 register */
81 u32 reserved; /* Reserved offset 0C */
82 u32 mas_data; /* SLINK_MAS_DATA_0 reg */
83 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
84 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
85 u32 status2; /* SLINK_STATUS2_0 reg */
86 u32 rsvd[56]; /* 0x20 to 0xFF reserved */
87 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
88 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
89 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
90 };
91
92 struct tegra30_spi_priv {
93 struct spi_regs *regs;
94 unsigned int freq;
95 unsigned int mode;
96 int periph_id;
97 int valid;
98 int last_transaction_us;
99 };
100
101 struct tegra_spi_slave {
102 struct spi_slave slave;
103 struct tegra30_spi_priv *ctrl;
104 };
105
tegra30_spi_of_to_plat(struct udevice * bus)106 static int tegra30_spi_of_to_plat(struct udevice *bus)
107 {
108 struct tegra_spi_plat *plat = dev_get_plat(bus);
109 const void *blob = gd->fdt_blob;
110 int node = dev_of_offset(bus);
111
112 plat->base = dev_read_addr(bus);
113 plat->periph_id = clock_decode_periph_id(bus);
114
115 if (plat->periph_id == PERIPH_ID_NONE) {
116 debug("%s: could not decode periph id %d\n", __func__,
117 plat->periph_id);
118 return -FDT_ERR_NOTFOUND;
119 }
120
121 /* Use 500KHz as a suitable default */
122 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
123 500000);
124 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
125 "spi-deactivate-delay", 0);
126 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
127 __func__, plat->base, plat->periph_id, plat->frequency,
128 plat->deactivate_delay_us);
129
130 return 0;
131 }
132
tegra30_spi_probe(struct udevice * bus)133 static int tegra30_spi_probe(struct udevice *bus)
134 {
135 struct tegra_spi_plat *plat = dev_get_plat(bus);
136 struct tegra30_spi_priv *priv = dev_get_priv(bus);
137
138 priv->regs = (struct spi_regs *)plat->base;
139
140 priv->last_transaction_us = timer_get_us();
141 priv->freq = plat->frequency;
142 priv->periph_id = plat->periph_id;
143
144 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
145 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
146 priv->freq);
147
148 return 0;
149 }
150
tegra30_spi_claim_bus(struct udevice * dev)151 static int tegra30_spi_claim_bus(struct udevice *dev)
152 {
153 struct udevice *bus = dev->parent;
154 struct tegra30_spi_priv *priv = dev_get_priv(bus);
155 struct spi_regs *regs = priv->regs;
156 u32 reg;
157
158 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
159 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
160 priv->freq);
161
162 /* Clear stale status here */
163 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
164 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
165 writel(reg, ®s->status);
166 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
167
168 /* Update the polarity bits */
169 if (priv->mode & SPI_CS_HIGH)
170 setbits_le32(&priv->regs->command,
171 cmd_cs_pol_bit[spi_chip_select(dev)]);
172 else
173 clrbits_le32(&priv->regs->command,
174 cmd_cs_pol_bit[spi_chip_select(dev)]);
175
176 /* Set master mode and sw controlled CS */
177 reg = readl(®s->command);
178 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
179 writel(reg, ®s->command);
180 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
181
182 return 0;
183 }
184
spi_cs_activate(struct udevice * dev)185 static void spi_cs_activate(struct udevice *dev)
186 {
187 struct udevice *bus = dev->parent;
188 struct tegra_spi_plat *pdata = dev_get_plat(bus);
189 struct tegra30_spi_priv *priv = dev_get_priv(bus);
190
191 /* If it's too soon to do another transaction, wait */
192 if (pdata->deactivate_delay_us &&
193 priv->last_transaction_us) {
194 ulong delay_us; /* The delay completed so far */
195 delay_us = timer_get_us() - priv->last_transaction_us;
196 if (delay_us < pdata->deactivate_delay_us)
197 udelay(pdata->deactivate_delay_us - delay_us);
198 }
199
200 /* CS is negated on Tegra, so drive a 1 to get a 0 */
201 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
202 }
203
spi_cs_deactivate(struct udevice * dev)204 static void spi_cs_deactivate(struct udevice *dev)
205 {
206 struct udevice *bus = dev->parent;
207 struct tegra_spi_plat *pdata = dev_get_plat(bus);
208 struct tegra30_spi_priv *priv = dev_get_priv(bus);
209
210 /* CS is negated on Tegra, so drive a 0 to get a 1 */
211 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
212
213 /* Remember time of this transaction so we can honour the bus delay */
214 if (pdata->deactivate_delay_us)
215 priv->last_transaction_us = timer_get_us();
216 }
217
tegra30_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * data_out,void * data_in,unsigned long flags)218 static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
219 const void *data_out, void *data_in,
220 unsigned long flags)
221 {
222 struct udevice *bus = dev->parent;
223 struct tegra30_spi_priv *priv = dev_get_priv(bus);
224 struct spi_regs *regs = priv->regs;
225 u32 reg, tmpdout, tmpdin = 0;
226 const u8 *dout = data_out;
227 u8 *din = data_in;
228 int num_bytes, overflow;
229 int ret = 0;
230
231 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
232 __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
233
234 num_bytes = DIV_ROUND_UP(bitlen, 8);
235 overflow = bitlen % 8;
236
237 reg = readl(®s->status);
238 writel(reg, ®s->status); /* Clear all SPI events via R/W */
239 debug("%s entry: STATUS = %08x\n", __func__, reg);
240
241 reg = readl(®s->status2);
242 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */
243 debug("%s entry: STATUS2 = %08x\n", __func__, reg);
244
245 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command));
246
247 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
248 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
249 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
250 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
251
252 if (flags & SPI_XFER_BEGIN)
253 spi_cs_activate(dev);
254
255 /* handle data in 32-bit chunks */
256 while (num_bytes > 0) {
257 int bytes;
258 int is_read = 0;
259 int tm, i;
260
261 tmpdout = 0;
262 bytes = (num_bytes > 4) ? 4 : num_bytes;
263
264 if (dout != NULL) {
265 for (i = 0; i < bytes; ++i)
266 tmpdout = (tmpdout << 8) | dout[i];
267 dout += bytes;
268 }
269
270 num_bytes -= bytes;
271
272 if (overflow && !num_bytes)
273 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK,
274 (bytes - 1) * 8 + overflow - 1);
275 else
276 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK,
277 bytes * 8 - 1);
278
279 writel(tmpdout, ®s->tx_fifo);
280 setbits_le32(®s->command, SLINK_CMD_GO);
281
282 /*
283 * Wait for SPI transmit FIFO to empty, or to time out.
284 * The RX FIFO status will be read and cleared last
285 */
286 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
287 u32 status;
288
289 status = readl(®s->status);
290
291 /* We can exit when we've had both RX and TX activity */
292 if (is_read && (status & SLINK_STAT_TXF_EMPTY))
293 break;
294
295 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
296 SLINK_STAT_RDY)
297 tm++;
298
299 else if (!(status & SLINK_STAT_RXF_EMPTY)) {
300 tmpdin = readl(®s->rx_fifo);
301 is_read = 1;
302
303 /* swap bytes read in */
304 if (din != NULL) {
305 for (i = bytes - 1; i >= 0; --i) {
306 din[i] = tmpdin & 0xff;
307 tmpdin >>= 8;
308 }
309 din += bytes;
310 }
311 }
312 }
313
314 if (tm >= SPI_TIMEOUT)
315 ret = tm;
316
317 /* clear ACK RDY, etc. bits */
318 writel(readl(®s->status), ®s->status);
319 }
320
321 if (flags & SPI_XFER_END)
322 spi_cs_deactivate(dev);
323
324 debug("%s: transfer ended. Value=%08x, status = %08x\n",
325 __func__, tmpdin, readl(®s->status));
326
327 if (ret) {
328 printf("%s: timeout during SPI transfer, tm %d\n",
329 __func__, ret);
330 return -1;
331 }
332
333 return 0;
334 }
335
tegra30_spi_set_speed(struct udevice * bus,uint speed)336 static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
337 {
338 struct tegra_spi_plat *plat = dev_get_plat(bus);
339 struct tegra30_spi_priv *priv = dev_get_priv(bus);
340
341 if (speed > plat->frequency)
342 speed = plat->frequency;
343 priv->freq = speed;
344 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
345
346 return 0;
347 }
348
tegra30_spi_set_mode(struct udevice * bus,uint mode)349 static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
350 {
351 struct tegra30_spi_priv *priv = dev_get_priv(bus);
352 struct spi_regs *regs = priv->regs;
353 u32 reg;
354
355 reg = readl(®s->command);
356
357 /* Set CPOL and CPHA */
358 reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
359 if (mode & SPI_CPHA)
360 reg |= SLINK_CMD_CK_SDA;
361
362 if (mode & SPI_CPOL)
363 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
364 else
365 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
366
367 writel(reg, ®s->command);
368
369 priv->mode = mode;
370 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
371
372 return 0;
373 }
374
375 static const struct dm_spi_ops tegra30_spi_ops = {
376 .claim_bus = tegra30_spi_claim_bus,
377 .xfer = tegra30_spi_xfer,
378 .set_speed = tegra30_spi_set_speed,
379 .set_mode = tegra30_spi_set_mode,
380 /*
381 * cs_info is not needed, since we require all chip selects to be
382 * in the device tree explicitly
383 */
384 };
385
386 static const struct udevice_id tegra30_spi_ids[] = {
387 { .compatible = "nvidia,tegra20-slink" },
388 { }
389 };
390
391 U_BOOT_DRIVER(tegra30_spi) = {
392 .name = "tegra20_slink",
393 .id = UCLASS_SPI,
394 .of_match = tegra30_spi_ids,
395 .ops = &tegra30_spi_ops,
396 .of_to_plat = tegra30_spi_of_to_plat,
397 .plat_auto = sizeof(struct tegra_spi_plat),
398 .priv_auto = sizeof(struct tegra30_spi_priv),
399 .probe = tegra30_spi_probe,
400 };
401