1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2010,2011
5 * Graeme Russ, <graeme.russ@gmail.com>
6 *
7 * Portions from Coreboot mainboard/google/link/romstage.c
8 * Copyright (C) 2007-2010 coresystems GmbH
9 * Copyright (C) 2011 Google Inc.
10 */
11
12 #define LOG_CATEGORY UCLASS_RAM
13
14 #include <dm.h>
15 #include <errno.h>
16 #include <fdtdec.h>
17 #include <init.h>
18 #include <log.h>
19 #include <malloc.h>
20 #include <net.h>
21 #include <rtc.h>
22 #include <spi.h>
23 #include <spi_flash.h>
24 #include <syscon.h>
25 #include <sysreset.h>
26 #include <asm/cpu.h>
27 #include <asm/processor.h>
28 #include <asm/gpio.h>
29 #include <asm/global_data.h>
30 #include <asm/intel_regs.h>
31 #include <asm/mrccache.h>
32 #include <asm/mrc_common.h>
33 #include <asm/mtrr.h>
34 #include <asm/pci.h>
35 #include <asm/report_platform.h>
36 #include <asm/arch/me.h>
37 #include <asm/arch/pei_data.h>
38 #include <asm/arch/pch.h>
39 #include <asm/post.h>
40 #include <asm/arch/sandybridge.h>
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 #define CMOS_OFFSET_MRC_SEED 152
45 #define CMOS_OFFSET_MRC_SEED_S3 156
46 #define CMOS_OFFSET_MRC_SEED_CHK 160
47
board_get_usable_ram_top(phys_size_t total_size)48 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
49 {
50 return mrc_common_board_get_usable_ram_top(total_size);
51 }
52
dram_init_banksize(void)53 int dram_init_banksize(void)
54 {
55 mrc_common_dram_init_banksize();
56
57 return 0;
58 }
59
read_seed_from_cmos(struct pei_data * pei_data)60 static int read_seed_from_cmos(struct pei_data *pei_data)
61 {
62 u16 c1, c2, checksum, seed_checksum;
63 struct udevice *dev;
64 int ret = 0;
65
66 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
67 if (ret) {
68 debug("Cannot find RTC: err=%d\n", ret);
69 return -ENODEV;
70 }
71
72 /*
73 * Read scrambler seeds from CMOS RAM. We don't want to store them in
74 * SPI flash since they change on every boot and that would wear down
75 * the flash too much. So we store these in CMOS and the large MRC
76 * data in SPI flash.
77 */
78 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
79 if (!ret) {
80 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3,
81 &pei_data->scrambler_seed_s3);
82 }
83 if (ret) {
84 debug("Failed to read from RTC %s\n", dev->name);
85 return ret;
86 }
87
88 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
89 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
90 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
91 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
92
93 /* Compute seed checksum and compare */
94 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
95 sizeof(u32));
96 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
97 sizeof(u32));
98 checksum = add_ip_checksums(sizeof(u32), c1, c2);
99
100 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
101 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
102
103 if (checksum != seed_checksum) {
104 debug("%s: invalid seed checksum\n", __func__);
105 pei_data->scrambler_seed = 0;
106 pei_data->scrambler_seed_s3 = 0;
107 return -EINVAL;
108 }
109
110 return 0;
111 }
112
prepare_mrc_cache(struct pei_data * pei_data)113 static int prepare_mrc_cache(struct pei_data *pei_data)
114 {
115 struct mrc_data_container *mrc_cache;
116 struct mrc_region entry;
117 int ret;
118
119 ret = read_seed_from_cmos(pei_data);
120 if (ret)
121 return ret;
122 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
123 if (ret)
124 return ret;
125 mrc_cache = mrccache_find_current(&entry);
126 if (!mrc_cache)
127 return -ENOENT;
128
129 pei_data->mrc_input = mrc_cache->data;
130 pei_data->mrc_input_len = mrc_cache->data_size;
131 debug("%s: at %p, size %x checksum %04x\n", __func__,
132 pei_data->mrc_input, pei_data->mrc_input_len,
133 mrc_cache->checksum);
134
135 return 0;
136 }
137
write_seeds_to_cmos(struct pei_data * pei_data)138 static int write_seeds_to_cmos(struct pei_data *pei_data)
139 {
140 u16 c1, c2, checksum;
141 struct udevice *dev;
142 int ret = 0;
143
144 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
145 if (ret) {
146 debug("Cannot find RTC: err=%d\n", ret);
147 return -ENODEV;
148 }
149
150 /* Save the MRC seed values to CMOS */
151 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
152 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
153 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
154
155 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
156 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
157 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
158
159 /* Save a simple checksum of the seed values */
160 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
161 sizeof(u32));
162 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
163 sizeof(u32));
164 checksum = add_ip_checksums(sizeof(u32), c1, c2);
165
166 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
167 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
168
169 return 0;
170 }
171
172 /* Use this hook to save our SDRAM parameters */
misc_init_r(void)173 int misc_init_r(void)
174 {
175 int ret;
176
177 ret = mrccache_save();
178 if (ret)
179 printf("Unable to save MRC data: %d\n", ret);
180
181 return 0;
182 }
183
post_system_agent_init(struct udevice * dev,struct udevice * me_dev,struct pei_data * pei_data)184 static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
185 struct pei_data *pei_data)
186 {
187 uint16_t done;
188
189 /*
190 * Send ME init done for SandyBridge here. This is done inside the
191 * SystemAgent binary on IvyBridge
192 */
193 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
194 done &= BASE_REV_MASK;
195 if (BASE_REV_SNB == done)
196 intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
197 else
198 intel_me_status(me_dev);
199
200 /* If PCIe init is skipped, set the PEG clock gating */
201 if (!pei_data->pcie_init)
202 setbits_le32(MCHBAR_REG(0x7010), 1);
203 }
204
recovery_mode_enabled(void)205 static int recovery_mode_enabled(void)
206 {
207 return false;
208 }
209
copy_spd(struct udevice * dev,struct pei_data * peid)210 static int copy_spd(struct udevice *dev, struct pei_data *peid)
211 {
212 const void *data;
213 int ret;
214
215 ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
216 if (ret) {
217 log_debug("Could not locate SPD (err=%d)\n", ret);
218 return ret;
219 }
220
221 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
222
223 return 0;
224 }
225
226 /**
227 * sdram_find() - Find available memory
228 *
229 * This is a bit complicated since on x86 there are system memory holes all
230 * over the place. We create a list of available memory blocks
231 *
232 * @dev: Northbridge device
233 */
sdram_find(struct udevice * dev)234 static int sdram_find(struct udevice *dev)
235 {
236 struct memory_info *info = &gd->arch.meminfo;
237 uint32_t tseg_base, uma_size, tolud;
238 uint64_t tom, me_base, touud;
239 uint64_t uma_memory_base = 0;
240 unsigned long long tomk;
241 uint16_t ggc;
242 u32 val;
243
244 /* Total Memory 2GB example:
245 *
246 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
247 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
248 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
249 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
250 * 7f200000 2034MB TOLUD
251 * 7f800000 2040MB MEBASE
252 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
253 * 80000000 2048MB TOM
254 * 100000000 4096MB-4102MB 6MB RAM (writeback)
255 *
256 * Total Memory 4GB example:
257 *
258 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
259 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
260 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
261 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
262 * afa00000 2810MB TOLUD
263 * ff800000 4088MB MEBASE
264 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
265 * 100000000 4096MB TOM
266 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
267 * 14fe00000 5368MB TOUUD
268 */
269
270 /* Top of Upper Usable DRAM, including remap */
271 dm_pci_read_config32(dev, TOUUD + 4, &val);
272 touud = (uint64_t)val << 32;
273 dm_pci_read_config32(dev, TOUUD, &val);
274 touud |= val;
275
276 /* Top of Lower Usable DRAM */
277 dm_pci_read_config32(dev, TOLUD, &tolud);
278
279 /* Top of Memory - does not account for any UMA */
280 dm_pci_read_config32(dev, 0xa4, &val);
281 tom = (uint64_t)val << 32;
282 dm_pci_read_config32(dev, 0xa0, &val);
283 tom |= val;
284
285 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
286
287 /* ME UMA needs excluding if total memory <4GB */
288 dm_pci_read_config32(dev, 0x74, &val);
289 me_base = (uint64_t)val << 32;
290 dm_pci_read_config32(dev, 0x70, &val);
291 me_base |= val;
292
293 debug("MEBASE %llx\n", me_base);
294
295 /* TODO: Get rid of all this shifting by 10 bits */
296 tomk = tolud >> 10;
297 if (me_base == tolud) {
298 /* ME is from MEBASE-TOM */
299 uma_size = (tom - me_base) >> 10;
300 /* Increment TOLUD to account for ME as RAM */
301 tolud += uma_size << 10;
302 /* UMA starts at old TOLUD */
303 uma_memory_base = tomk * 1024ULL;
304 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
305 }
306
307 /* Graphics memory comes next */
308 dm_pci_read_config16(dev, GGC, &ggc);
309 if (!(ggc & 2)) {
310 debug("IGD decoded, subtracting ");
311
312 /* Graphics memory */
313 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
314 debug("%uM UMA", uma_size >> 10);
315 tomk -= uma_size;
316 uma_memory_base = tomk * 1024ULL;
317
318 /* GTT Graphics Stolen Memory Size (GGMS) */
319 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
320 tomk -= uma_size;
321 uma_memory_base = tomk * 1024ULL;
322 debug(" and %uM GTT\n", uma_size >> 10);
323 }
324
325 /* Calculate TSEG size from its base which must be below GTT */
326 dm_pci_read_config32(dev, 0xb8, &tseg_base);
327 uma_size = (uma_memory_base - tseg_base) >> 10;
328 tomk -= uma_size;
329 uma_memory_base = tomk * 1024ULL;
330 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
331
332 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
333
334 /* Report the memory regions */
335 mrc_add_memory_area(info, 1 << 20, 2 << 28);
336 mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
337 mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
338 mrc_add_memory_area(info, 1ULL << 32, touud);
339
340 /* Add MTRRs for memory */
341 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
342 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
343 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
344 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
345 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
346 32 << 20);
347
348 /*
349 * If >= 4GB installed then memory from TOLUD to 4GB
350 * is remapped above TOM, TOUUD will account for both
351 */
352 if (touud > (1ULL << 32ULL)) {
353 debug("Available memory above 4GB: %lluM\n",
354 (touud >> 20) - 4096);
355 }
356
357 return 0;
358 }
359
rcba_config(void)360 static void rcba_config(void)
361 {
362 /*
363 * GFX INTA -> PIRQA (MSI)
364 * D28IP_P3IP WLAN INTA -> PIRQB
365 * D29IP_E1P EHCI1 INTA -> PIRQD
366 * D26IP_E2P EHCI2 INTA -> PIRQF
367 * D31IP_SIP SATA INTA -> PIRQF (MSI)
368 * D31IP_SMIP SMBUS INTB -> PIRQH
369 * D31IP_TTIP THRT INTC -> PIRQA
370 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
371 *
372 * TRACKPAD -> PIRQE (Edge Triggered)
373 * TOUCHSCREEN -> PIRQG (Edge Triggered)
374 */
375
376 /* Device interrupt pin register (board specific) */
377 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
378 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
379 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
380 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
381 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
382 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
383 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
384 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
385 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
386
387 /* Device interrupt route registers */
388 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
389 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
390 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
391 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
392 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
393 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
394 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
395
396 /* Enable IOAPIC (generic) */
397 writew(0x0100, RCB_REG(OIC));
398 /* PCH BWG says to read back the IOAPIC enable register */
399 (void)readw(RCB_REG(OIC));
400
401 /* Disable unused devices (board specific) */
402 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
403 }
404
dram_init(void)405 int dram_init(void)
406 {
407 struct pei_data _pei_data __aligned(8) = {
408 .pei_version = PEI_VERSION,
409 .mchbar = MCH_BASE_ADDRESS,
410 .dmibar = DEFAULT_DMIBAR,
411 .epbar = DEFAULT_EPBAR,
412 .pciexbar = CONFIG_PCIE_ECAM_BASE,
413 .smbusbar = SMBUS_IO_BASE,
414 .wdbbar = 0x4000000,
415 .wdbsize = 0x1000,
416 .hpet_address = CONFIG_HPET_ADDRESS,
417 .rcba = DEFAULT_RCBABASE,
418 .pmbase = DEFAULT_PMBASE,
419 .gpiobase = DEFAULT_GPIOBASE,
420 .thermalbase = 0xfed08000,
421 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
422 .tseg_size = CONFIG_SMM_TSEG_SIZE,
423 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
424 .ec_present = 1,
425 .ddr3lv_support = 1,
426 /*
427 * 0 = leave channel enabled
428 * 1 = disable dimm 0 on channel
429 * 2 = disable dimm 1 on channel
430 * 3 = disable dimm 0+1 on channel
431 */
432 .dimm_channel0_disabled = 2,
433 .dimm_channel1_disabled = 2,
434 .max_ddr3_freq = 1600,
435 .usb_port_config = {
436 /*
437 * Empty and onboard Ports 0-7, set to un-used pin
438 * OC3
439 */
440 { 0, 3, 0x0000 }, /* P0= Empty */
441 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
442 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
443 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
444 { 0, 3, 0x0000 }, /* P4= Empty */
445 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
446 { 0, 3, 0x0000 }, /* P6= Empty */
447 { 0, 3, 0x0000 }, /* P7= Empty */
448 /*
449 * Empty and onboard Ports 8-13, set to un-used pin
450 * OC4
451 */
452 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
453 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
454 { 0, 4, 0x0000 }, /* P10= Empty */
455 { 0, 4, 0x0000 }, /* P11= Empty */
456 { 0, 4, 0x0000 }, /* P12= Empty */
457 { 0, 4, 0x0000 }, /* P13= Empty */
458 },
459 };
460 struct pei_data *pei_data = &_pei_data;
461 struct udevice *dev, *me_dev;
462 int ret;
463
464 /* We need the pinctrl set up early */
465 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
466 if (ret) {
467 debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret);
468 return ret;
469 }
470
471 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
472 if (ret) {
473 debug("%s: Could not get northbridge (ret=%d)\n", __func__,
474 ret);
475 return ret;
476 }
477 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
478 if (ret) {
479 debug("%s: Could not get ME (ret=%d)\n", __func__, ret);
480 return ret;
481 }
482 ret = copy_spd(dev, pei_data);
483 if (ret) {
484 debug("%s: Could not get SPD (ret=%d)\n", __func__, ret);
485 return ret;
486 }
487 pei_data->boot_mode = gd->arch.pei_boot_mode;
488 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
489 debug("mrc_input %p\n", pei_data->mrc_input);
490
491 /*
492 * Do not pass MRC data in for recovery mode boot,
493 * Always pass it in for S3 resume.
494 */
495 if (!recovery_mode_enabled() ||
496 pei_data->boot_mode == PEI_BOOT_RESUME) {
497 ret = prepare_mrc_cache(pei_data);
498 if (ret)
499 debug("prepare_mrc_cache failed: %d\n", ret);
500 }
501
502 /* If MRC data is not found we cannot continue S3 resume. */
503 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
504 debug("Giving up in sdram_initialize: No MRC data\n");
505 sysreset_walk_halt(SYSRESET_COLD);
506 }
507
508 /* Pass console handler in pei_data */
509 pei_data->tx_byte = sdram_console_tx_byte;
510
511 /* Wait for ME to be ready */
512 ret = intel_early_me_init(me_dev);
513 if (ret) {
514 debug("%s: Could not init ME (ret=%d)\n", __func__, ret);
515 return ret;
516 }
517 ret = intel_early_me_uma_size(me_dev);
518 if (ret < 0) {
519 debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret);
520 return ret;
521 }
522
523 ret = mrc_common_init(dev, pei_data, false);
524 if (ret) {
525 debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret);
526 return ret;
527 }
528
529 ret = sdram_find(dev);
530 if (ret) {
531 debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret);
532 return ret;
533 }
534 gd->ram_size = gd->arch.meminfo.total_32bit_memory;
535
536 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
537 pei_data->mrc_output);
538
539 post_system_agent_init(dev, me_dev, pei_data);
540 report_memory_config();
541
542 /* S3 resume: don't save scrambler seed or MRC data */
543 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
544 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
545
546 /*
547 * This will be copied to SDRAM in reserve_arch(), then written
548 * to SPI flash in mrccache_save()
549 */
550 mrc->buf = (char *)pei_data->mrc_output;
551 mrc->len = pei_data->mrc_output_len;
552 ret = write_seeds_to_cmos(pei_data);
553 if (ret)
554 debug("Failed to write seeds to CMOS: %d\n", ret);
555 }
556
557 writew(0xCAFE, MCHBAR_REG(SSKPD));
558 if (ret)
559 return ret;
560
561 rcba_config();
562
563 return 0;
564 }
565