1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2012 DENX Software Engineering GmbH 4 * Heiko Schocher <hs@denx.de> 5 */ 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 chosen { }; 12 aliases { }; 13 14 memory@c0000000 { 15 device_type = "memory"; 16 reg = <0xc0000000 0x0>; 17 }; 18 19 arm { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 intc: interrupt-controller@fffee000 { 24 compatible = "ti,cp-intc"; 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 ti,intc-size = <101>; 28 reg = <0xfffee000 0x2000>; 29 }; 30 }; 31 clocks: clocks { 32 ref_clk: ref_clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-output-names = "ref_clk"; 36 }; 37 sata_refclk: sata_refclk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-output-names = "sata_refclk"; 41 status = "disabled"; 42 }; 43 usb_refclkin: usb_refclkin { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-output-names = "usb_refclkin"; 47 status = "disabled"; 48 }; 49 }; 50 dsp: dsp@11800000 { 51 compatible = "ti,da850-dsp"; 52 reg = <0x11800000 0x40000>, 53 <0x11e00000 0x8000>, 54 <0x11f00000 0x8000>, 55 <0x01c14044 0x4>, 56 <0x01c14174 0x8>; 57 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; 58 interrupt-parent = <&intc>; 59 interrupts = <28>; 60 clocks = <&psc0 15>; 61 resets = <&psc0 15>; 62 status = "disabled"; 63 }; 64 soc@1c00000 { 65 compatible = "simple-bus"; 66 model = "da850"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges = <0x0 0x01c00000 0x400000>; 70 interrupt-parent = <&intc>; 71 72 psc0: clock-controller@10000 { 73 compatible = "ti,da850-psc0"; 74 reg = <0x10000 0x1000>; 75 #clock-cells = <1>; 76 #reset-cells = <1>; 77 #power-domain-cells = <1>; 78 clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, 79 <&pll0_sysclk 4>, <&pll0_sysclk 6>, 80 <&async1_clk>; 81 clock-names = "pll0_sysclk1", "pll0_sysclk2", 82 "pll0_sysclk4", "pll0_sysclk6", 83 "async1"; 84 }; 85 pll0: clock-controller@11000 { 86 compatible = "ti,da850-pll0"; 87 reg = <0x11000 0x1000>; 88 clocks = <&ref_clk>, <&pll1_sysclk 3>; 89 clock-names = "clksrc", "extclksrc"; 90 91 pll0_pllout: pllout { 92 #clock-cells = <0>; 93 }; 94 pll0_sysclk: sysclk { 95 #clock-cells = <1>; 96 }; 97 pll0_auxclk: auxclk { 98 #clock-cells = <0>; 99 }; 100 pll0_obsclk: obsclk { 101 #clock-cells = <0>; 102 }; 103 }; 104 pmx_core: pinmux@14120 { 105 compatible = "pinctrl-single"; 106 reg = <0x14120 0x50>; 107 #pinctrl-cells = <2>; 108 pinctrl-single,bit-per-mux; 109 pinctrl-single,register-width = <32>; 110 pinctrl-single,function-mask = <0xf>; 111 /* pin base, nr pins & gpio function */ 112 pinctrl-single,gpio-range = <&range 0 17 0x8>, 113 <&range 17 8 0x4>, 114 <&range 26 8 0x4>, 115 <&range 34 80 0x8>, 116 <&range 129 31 0x8>; 117 status = "disabled"; 118 119 range: gpio-range { 120 #pinctrl-single,gpio-range-cells = <3>; 121 }; 122 123 serial0_rtscts_pins: pinmux_serial0_rtscts_pins { 124 pinctrl-single,bits = < 125 /* UART0_RTS UART0_CTS */ 126 0x0c 0x22000000 0xff000000 127 >; 128 }; 129 serial0_rxtx_pins: pinmux_serial0_rxtx_pins { 130 pinctrl-single,bits = < 131 /* UART0_TXD UART0_RXD */ 132 0x0c 0x00220000 0x00ff0000 133 >; 134 }; 135 serial1_rtscts_pins: pinmux_serial1_rtscts_pins { 136 pinctrl-single,bits = < 137 /* UART1_CTS UART1_RTS */ 138 0x00 0x00440000 0x00ff0000 139 >; 140 }; 141 serial1_rxtx_pins: pinmux_serial1_rxtx_pins { 142 pinctrl-single,bits = < 143 /* UART1_TXD UART1_RXD */ 144 0x10 0x22000000 0xff000000 145 >; 146 }; 147 serial2_rtscts_pins: pinmux_serial2_rtscts_pins { 148 pinctrl-single,bits = < 149 /* UART2_CTS UART2_RTS */ 150 0x00 0x44000000 0xff000000 151 >; 152 }; 153 serial2_rxtx_pins: pinmux_serial2_rxtx_pins { 154 pinctrl-single,bits = < 155 /* UART2_TXD UART2_RXD */ 156 0x10 0x00220000 0x00ff0000 157 >; 158 }; 159 i2c0_pins: pinmux_i2c0_pins { 160 pinctrl-single,bits = < 161 /* I2C0_SDA,I2C0_SCL */ 162 0x10 0x00002200 0x0000ff00 163 >; 164 }; 165 i2c1_pins: pinmux_i2c1_pins { 166 pinctrl-single,bits = < 167 /* I2C1_SDA, I2C1_SCL */ 168 0x10 0x00440000 0x00ff0000 169 >; 170 }; 171 mmc0_pins: pinmux_mmc_pins { 172 pinctrl-single,bits = < 173 /* MMCSD0_DAT[3] MMCSD0_DAT[2] 174 * MMCSD0_DAT[1] MMCSD0_DAT[0] 175 * MMCSD0_CMD MMCSD0_CLK 176 */ 177 0x28 0x00222222 0x00ffffff 178 >; 179 }; 180 ehrpwm0a_pins: pinmux_ehrpwm0a_pins { 181 pinctrl-single,bits = < 182 /* EPWM0A */ 183 0xc 0x00000002 0x0000000f 184 >; 185 }; 186 ehrpwm0b_pins: pinmux_ehrpwm0b_pins { 187 pinctrl-single,bits = < 188 /* EPWM0B */ 189 0xc 0x00000020 0x000000f0 190 >; 191 }; 192 ehrpwm1a_pins: pinmux_ehrpwm1a_pins { 193 pinctrl-single,bits = < 194 /* EPWM1A */ 195 0x14 0x00000002 0x0000000f 196 >; 197 }; 198 ehrpwm1b_pins: pinmux_ehrpwm1b_pins { 199 pinctrl-single,bits = < 200 /* EPWM1B */ 201 0x14 0x00000020 0x000000f0 202 >; 203 }; 204 ecap0_pins: pinmux_ecap0_pins { 205 pinctrl-single,bits = < 206 /* ECAP0_APWM0 */ 207 0x8 0x20000000 0xf0000000 208 >; 209 }; 210 ecap1_pins: pinmux_ecap1_pins { 211 pinctrl-single,bits = < 212 /* ECAP1_APWM1 */ 213 0x4 0x40000000 0xf0000000 214 >; 215 }; 216 ecap2_pins: pinmux_ecap2_pins { 217 pinctrl-single,bits = < 218 /* ECAP2_APWM2 */ 219 0x4 0x00000004 0x0000000f 220 >; 221 }; 222 spi0_pins: pinmux_spi0_pins { 223 pinctrl-single,bits = < 224 /* SIMO, SOMI, CLK */ 225 0xc 0x00001101 0x0000ff0f 226 >; 227 }; 228 spi0_cs0_pin: pinmux_spi0_cs0 { 229 pinctrl-single,bits = < 230 /* CS0 */ 231 0x10 0x00000010 0x000000f0 232 >; 233 }; 234 spi0_cs3_pin: pinmux_spi0_cs3_pin { 235 pinctrl-single,bits = < 236 /* CS3 */ 237 0xc 0x01000000 0x0f000000 238 >; 239 }; 240 spi1_pins: pinmux_spi1_pins { 241 pinctrl-single,bits = < 242 /* SIMO, SOMI, CLK */ 243 0x14 0x00110100 0x00ff0f00 244 >; 245 }; 246 spi1_cs0_pin: pinmux_spi1_cs0 { 247 pinctrl-single,bits = < 248 /* CS0 */ 249 0x14 0x00000010 0x000000f0 250 >; 251 }; 252 mdio_pins: pinmux_mdio_pins { 253 pinctrl-single,bits = < 254 /* MDIO_CLK, MDIO_D */ 255 0x10 0x00000088 0x000000ff 256 >; 257 }; 258 mii_pins: pinmux_mii_pins { 259 pinctrl-single,bits = < 260 /* 261 * MII_TXEN, MII_TXCLK, MII_COL 262 * MII_TXD_3, MII_TXD_2, MII_TXD_1 263 * MII_TXD_0 264 */ 265 0x8 0x88888880 0xfffffff0 266 /* 267 * MII_RXER, MII_CRS, MII_RXCLK 268 * MII_RXDV, MII_RXD_3, MII_RXD_2 269 * MII_RXD_1, MII_RXD_0 270 */ 271 0xc 0x88888888 0xffffffff 272 >; 273 }; 274 lcd_pins: pinmux_lcd_pins { 275 pinctrl-single,bits = < 276 /* 277 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], 278 * LCD_D[6], LCD_D[7] 279 */ 280 0x40 0x22222200 0xffffff00 281 /* 282 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], 283 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] 284 */ 285 0x44 0x22222222 0xffffffff 286 /* LCD_D[8], LCD_D[9] */ 287 0x48 0x00000022 0x000000ff 288 289 /* LCD_PCLK */ 290 0x48 0x02000000 0x0f000000 291 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ 292 0x4c 0x02000022 0x0f0000ff 293 >; 294 }; 295 vpif_capture_pins: vpif_capture_pins { 296 pinctrl-single,bits = < 297 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ 298 0x38 0x11111111 0xffffffff 299 /* VP_DIN[10..15,0..1] */ 300 0x3c 0x11111111 0xffffffff 301 /* VP_DIN[8..9] */ 302 0x40 0x00000011 0x000000ff 303 >; 304 }; 305 vpif_display_pins: vpif_display_pins { 306 pinctrl-single,bits = < 307 /* VP_DOUT[2..7] */ 308 0x40 0x11111100 0xffffff00 309 /* VP_DOUT[10..15,0..1] */ 310 0x44 0x11111111 0xffffffff 311 /* VP_DOUT[8..9] */ 312 0x48 0x00000011 0x000000ff 313 /* 314 * VP_CLKOUT3, VP_CLKIN3, 315 * VP_CLKOUT2, VP_CLKIN2 316 */ 317 0x4c 0x00111100 0x00ffff00 318 >; 319 }; 320 }; 321 prictrl: priority-controller@14110 { 322 compatible = "ti,da850-mstpri"; 323 reg = <0x14110 0x0c>; 324 status = "disabled"; 325 }; 326 cfgchip: chip-controller@1417c { 327 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; 328 reg = <0x1417c 0x14>; 329 330 usb_phy: usb-phy { 331 compatible = "ti,da830-usb-phy"; 332 #phy-cells = <1>; 333 clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; 334 clock-names = "usb0_clk48", "usb1_clk48"; 335 status = "disabled"; 336 }; 337 usb_phy_clk: usb-phy-clocks { 338 compatible = "ti,da830-usb-phy-clocks"; 339 #clock-cells = <1>; 340 clocks = <&psc1 1>, <&usb_refclkin>, 341 <&pll0_auxclk>; 342 clock-names = "fck", "usb_refclkin", "auxclk"; 343 }; 344 ehrpwm_tbclk: ehrpwm_tbclk { 345 compatible = "ti,da830-tbclksync"; 346 #clock-cells = <0>; 347 clocks = <&psc1 17>; 348 clock-names = "fck"; 349 }; 350 div4p5_clk: div4.5 { 351 compatible = "ti,da830-div4p5ena"; 352 #clock-cells = <0>; 353 clocks = <&pll0_pllout>; 354 clock-names = "pll0_pllout"; 355 }; 356 async1_clk: async1 { 357 compatible = "ti,da850-async1-clksrc"; 358 #clock-cells = <0>; 359 clocks = <&pll0_sysclk 3>, <&div4p5_clk>; 360 clock-names = "pll0_sysclk3", "div4.5"; 361 }; 362 async3_clk: async3 { 363 compatible = "ti,da850-async3-clksrc"; 364 #clock-cells = <0>; 365 clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; 366 clock-names = "pll0_sysclk2", "pll1_sysclk2"; 367 }; 368 }; 369 edma0: edma@0 { 370 compatible = "ti,edma3-tpcc"; 371 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ 372 reg = <0x0 0x8000>; 373 reg-names = "edma3_cc"; 374 interrupts = <11 12>; 375 interrupt-names = "edma3_ccint", "edma3_ccerrint"; 376 #dma-cells = <2>; 377 378 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; 379 power-domains = <&psc0 0>; 380 }; 381 edma0_tptc0: tptc@8000 { 382 compatible = "ti,edma3-tptc"; 383 reg = <0x8000 0x400>; 384 interrupts = <13>; 385 interrupt-names = "edm3_tcerrint"; 386 power-domains = <&psc0 1>; 387 }; 388 edma0_tptc1: tptc@8400 { 389 compatible = "ti,edma3-tptc"; 390 reg = <0x8400 0x400>; 391 interrupts = <32>; 392 interrupt-names = "edm3_tcerrint"; 393 power-domains = <&psc0 2>; 394 }; 395 edma1: edma@230000 { 396 compatible = "ti,edma3-tpcc"; 397 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ 398 reg = <0x230000 0x8000>; 399 reg-names = "edma3_cc"; 400 interrupts = <93 94>; 401 interrupt-names = "edma3_ccint", "edma3_ccerrint"; 402 #dma-cells = <2>; 403 404 ti,tptcs = <&edma1_tptc0 7>; 405 power-domains = <&psc1 0>; 406 }; 407 edma1_tptc0: tptc@238000 { 408 compatible = "ti,edma3-tptc"; 409 reg = <0x238000 0x400>; 410 interrupts = <95>; 411 interrupt-names = "edm3_tcerrint"; 412 power-domains = <&psc1 21>; 413 }; 414 serial0: serial@42000 { 415 compatible = "ti,da830-uart", "ns16550a"; 416 reg = <0x42000 0x100>; 417 reg-io-width = <4>; 418 reg-shift = <2>; 419 interrupts = <25>; 420 clocks = <&psc0 9>; 421 power-domains = <&psc0 9>; 422 status = "disabled"; 423 }; 424 serial1: serial@10c000 { 425 compatible = "ti,da830-uart", "ns16550a"; 426 reg = <0x10c000 0x100>; 427 reg-io-width = <4>; 428 reg-shift = <2>; 429 interrupts = <53>; 430 clocks = <&psc1 12>; 431 power-domains = <&psc1 12>; 432 status = "disabled"; 433 }; 434 serial2: serial@10d000 { 435 compatible = "ti,da830-uart", "ns16550a"; 436 reg = <0x10d000 0x100>; 437 reg-io-width = <4>; 438 reg-shift = <2>; 439 interrupts = <61>; 440 clocks = <&psc1 13>; 441 power-domains = <&psc1 13>; 442 status = "disabled"; 443 }; 444 rtc0: rtc@23000 { 445 compatible = "ti,da830-rtc"; 446 reg = <0x23000 0x1000>; 447 interrupts = <19 448 19>; 449 clocks = <&pll0_auxclk>; 450 clock-names = "int-clk"; 451 status = "disabled"; 452 }; 453 i2c0: i2c@22000 { 454 compatible = "ti,davinci-i2c"; 455 reg = <0x22000 0x1000>; 456 interrupts = <15>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&pll0_auxclk>; 460 status = "disabled"; 461 }; 462 i2c1: i2c@228000 { 463 compatible = "ti,davinci-i2c"; 464 reg = <0x228000 0x1000>; 465 interrupts = <51>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&psc1 11>; 469 power-domains = <&psc1 11>; 470 status = "disabled"; 471 }; 472 clocksource: timer@20000 { 473 compatible = "ti,da830-timer"; 474 reg = <0x20000 0x1000>; 475 interrupts = <21>, <22>; 476 interrupt-names = "tint12", "tint34"; 477 clocks = <&pll0_auxclk>; 478 }; 479 wdt: wdt@21000 { 480 compatible = "ti,davinci-wdt"; 481 reg = <0x21000 0x1000>; 482 clocks = <&pll0_auxclk>; 483 status = "disabled"; 484 }; 485 mmc0: mmc@40000 { 486 compatible = "ti,da830-mmc"; 487 reg = <0x40000 0x1000>; 488 cap-sd-highspeed; 489 cap-mmc-highspeed; 490 interrupts = <16>; 491 dmas = <&edma0 16 0>, <&edma0 17 0>; 492 dma-names = "rx", "tx"; 493 clocks = <&psc0 5>; 494 status = "disabled"; 495 }; 496 vpif: video@217000 { 497 compatible = "ti,da850-vpif"; 498 reg = <0x217000 0x1000>; 499 interrupts = <92>; 500 power-domains = <&psc1 9>; 501 status = "disabled"; 502 503 /* VPIF capture port */ 504 port@0 { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 }; 508 509 /* VPIF display port */ 510 port@1 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 }; 514 }; 515 mmc1: mmc@21b000 { 516 compatible = "ti,da830-mmc"; 517 reg = <0x21b000 0x1000>; 518 cap-sd-highspeed; 519 cap-mmc-highspeed; 520 interrupts = <72>; 521 dmas = <&edma1 28 0>, <&edma1 29 0>; 522 dma-names = "rx", "tx"; 523 clocks = <&psc1 18>; 524 status = "disabled"; 525 }; 526 ehrpwm0: pwm@300000 { 527 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", 528 "ti,am33xx-ehrpwm"; 529 #pwm-cells = <3>; 530 reg = <0x300000 0x2000>; 531 clocks = <&psc1 17>, <&ehrpwm_tbclk>; 532 clock-names = "fck", "tbclk"; 533 power-domains = <&psc1 17>; 534 status = "disabled"; 535 }; 536 ehrpwm1: pwm@302000 { 537 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", 538 "ti,am33xx-ehrpwm"; 539 #pwm-cells = <3>; 540 reg = <0x302000 0x2000>; 541 clocks = <&psc1 17>, <&ehrpwm_tbclk>; 542 clock-names = "fck", "tbclk"; 543 power-domains = <&psc1 17>; 544 status = "disabled"; 545 }; 546 ecap0: pwm@306000 { 547 compatible = "ti,da850-ecap", "ti,am3352-ecap", 548 "ti,am33xx-ecap"; 549 #pwm-cells = <3>; 550 reg = <0x306000 0x80>; 551 clocks = <&psc1 20>; 552 clock-names = "fck"; 553 power-domains = <&psc1 20>; 554 status = "disabled"; 555 }; 556 ecap1: pwm@307000 { 557 compatible = "ti,da850-ecap", "ti,am3352-ecap", 558 "ti,am33xx-ecap"; 559 #pwm-cells = <3>; 560 reg = <0x307000 0x80>; 561 clocks = <&psc1 20>; 562 clock-names = "fck"; 563 power-domains = <&psc1 20>; 564 status = "disabled"; 565 }; 566 ecap2: pwm@308000 { 567 compatible = "ti,da850-ecap", "ti,am3352-ecap", 568 "ti,am33xx-ecap"; 569 #pwm-cells = <3>; 570 reg = <0x308000 0x80>; 571 clocks = <&psc1 20>; 572 clock-names = "fck"; 573 power-domains = <&psc1 20>; 574 status = "disabled"; 575 }; 576 spi0: spi@41000 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 compatible = "ti,da830-spi"; 580 reg = <0x41000 0x1000>; 581 num-cs = <6>; 582 ti,davinci-spi-intr-line = <1>; 583 interrupts = <20>; 584 dmas = <&edma0 14 0>, <&edma0 15 0>; 585 dma-names = "rx", "tx"; 586 clocks = <&psc0 4>; 587 power-domains = <&psc0 4>; 588 status = "disabled"; 589 }; 590 spi1: spi@30e000 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 compatible = "ti,da830-spi"; 594 reg = <0x30e000 0x1000>; 595 num-cs = <4>; 596 ti,davinci-spi-intr-line = <1>; 597 interrupts = <56>; 598 dmas = <&edma0 18 0>, <&edma0 19 0>; 599 dma-names = "rx", "tx"; 600 clocks = <&psc1 10>; 601 power-domains = <&psc1 10>; 602 status = "disabled"; 603 }; 604 usb0: usb@200000 { 605 compatible = "ti,da830-musb"; 606 reg = <0x200000 0x1000>; 607 ranges; 608 interrupts = <58>; 609 interrupt-names = "mc"; 610 dr_mode = "otg"; 611 phys = <&usb_phy 0>; 612 phy-names = "usb-phy"; 613 clocks = <&psc1 1>; 614 clock-ranges; 615 status = "disabled"; 616 617 #address-cells = <1>; 618 #size-cells = <1>; 619 620 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 621 &cppi41dma 2 0 &cppi41dma 3 0 622 &cppi41dma 0 1 &cppi41dma 1 1 623 &cppi41dma 2 1 &cppi41dma 3 1>; 624 dma-names = 625 "rx1", "rx2", "rx3", "rx4", 626 "tx1", "tx2", "tx3", "tx4"; 627 628 cppi41dma: dma-controller@201000 { 629 compatible = "ti,da830-cppi41"; 630 reg = <0x201000 0x1000 631 0x202000 0x1000 632 0x204000 0x4000>; 633 reg-names = "controller", 634 "scheduler", "queuemgr"; 635 interrupts = <58>; 636 #dma-cells = <2>; 637 #dma-channels = <4>; 638 power-domains = <&psc1 1>; 639 status = "okay"; 640 }; 641 }; 642 sata: sata@218000 { 643 compatible = "ti,da850-ahci"; 644 reg = <0x218000 0x2000>, <0x22c018 0x4>; 645 interrupts = <67>; 646 clocks = <&psc1 8>, <&sata_refclk>; 647 clock-names = "fck", "refclk"; 648 status = "disabled"; 649 }; 650 pll1: clock-controller@21a000 { 651 compatible = "ti,da850-pll1"; 652 reg = <0x21a000 0x1000>; 653 clocks = <&ref_clk>; 654 clock-names = "clksrc"; 655 656 pll1_sysclk: sysclk { 657 #clock-cells = <1>; 658 }; 659 pll1_obsclk: obsclk { 660 #clock-cells = <0>; 661 }; 662 }; 663 mdio: mdio@224000 { 664 compatible = "ti,davinci_mdio"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 reg = <0x224000 0x1000>; 668 clocks = <&psc1 5>; 669 clock-names = "fck"; 670 power-domains = <&psc1 5>; 671 status = "disabled"; 672 }; 673 eth0: ethernet@220000 { 674 compatible = "ti,davinci-dm6467-emac"; 675 reg = <0x220000 0x4000>; 676 ti,davinci-ctrl-reg-offset = <0x3000>; 677 ti,davinci-ctrl-mod-reg-offset = <0x2000>; 678 ti,davinci-ctrl-ram-offset = <0>; 679 ti,davinci-ctrl-ram-size = <0x2000>; 680 local-mac-address = [ 00 00 00 00 00 00 ]; 681 interrupts = <33 682 34 683 35 684 36 685 >; 686 clocks = <&psc1 5>; 687 power-domains = <&psc1 5>; 688 status = "disabled"; 689 }; 690 usb1: usb@225000 { 691 compatible = "ti,da830-ohci"; 692 reg = <0x225000 0x1000>; 693 interrupts = <59>; 694 phys = <&usb_phy 1>; 695 phy-names = "usb-phy"; 696 clocks = <&psc1 2>; 697 status = "disabled"; 698 }; 699 gpio: gpio@226000 { 700 compatible = "ti,dm6441-gpio"; 701 gpio-controller; 702 #gpio-cells = <2>; 703 reg = <0x226000 0x1000>; 704 interrupts = <42 43 44 45 46 47 48 49 50>; 705 ti,ngpio = <144>; 706 ti,davinci-gpio-unbanked = <0>; 707 clocks = <&psc1 3>; 708 clock-names = "gpio"; 709 status = "disabled"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 gpio-ranges = <&pmx_core 0 15 1>, 713 <&pmx_core 1 14 1>, 714 <&pmx_core 2 13 1>, 715 <&pmx_core 3 12 1>, 716 <&pmx_core 4 11 1>, 717 <&pmx_core 5 10 1>, 718 <&pmx_core 6 9 1>, 719 <&pmx_core 7 8 1>, 720 <&pmx_core 8 7 1>, 721 <&pmx_core 9 6 1>, 722 <&pmx_core 10 5 1>, 723 <&pmx_core 11 4 1>, 724 <&pmx_core 12 3 1>, 725 <&pmx_core 13 2 1>, 726 <&pmx_core 14 1 1>, 727 <&pmx_core 15 0 1>, 728 <&pmx_core 16 39 1>, 729 <&pmx_core 17 38 1>, 730 <&pmx_core 18 37 1>, 731 <&pmx_core 19 36 1>, 732 <&pmx_core 20 35 1>, 733 <&pmx_core 21 34 1>, 734 <&pmx_core 22 33 1>, 735 <&pmx_core 23 32 1>, 736 <&pmx_core 24 24 1>, 737 <&pmx_core 25 22 1>, 738 <&pmx_core 26 21 1>, 739 <&pmx_core 27 20 1>, 740 <&pmx_core 28 19 1>, 741 <&pmx_core 29 18 1>, 742 <&pmx_core 30 17 1>, 743 <&pmx_core 31 16 1>, 744 <&pmx_core 32 55 1>, 745 <&pmx_core 33 54 1>, 746 <&pmx_core 34 53 1>, 747 <&pmx_core 35 52 1>, 748 <&pmx_core 36 51 1>, 749 <&pmx_core 37 50 1>, 750 <&pmx_core 38 49 1>, 751 <&pmx_core 39 48 1>, 752 <&pmx_core 40 47 1>, 753 <&pmx_core 41 46 1>, 754 <&pmx_core 42 45 1>, 755 <&pmx_core 43 44 1>, 756 <&pmx_core 44 43 1>, 757 <&pmx_core 45 42 1>, 758 <&pmx_core 46 41 1>, 759 <&pmx_core 47 40 1>, 760 <&pmx_core 48 71 1>, 761 <&pmx_core 49 70 1>, 762 <&pmx_core 50 69 1>, 763 <&pmx_core 51 68 1>, 764 <&pmx_core 52 67 1>, 765 <&pmx_core 53 66 1>, 766 <&pmx_core 54 65 1>, 767 <&pmx_core 55 64 1>, 768 <&pmx_core 56 63 1>, 769 <&pmx_core 57 62 1>, 770 <&pmx_core 58 61 1>, 771 <&pmx_core 59 60 1>, 772 <&pmx_core 60 59 1>, 773 <&pmx_core 61 58 1>, 774 <&pmx_core 62 57 1>, 775 <&pmx_core 63 56 1>, 776 <&pmx_core 64 87 1>, 777 <&pmx_core 65 86 1>, 778 <&pmx_core 66 85 1>, 779 <&pmx_core 67 84 1>, 780 <&pmx_core 68 83 1>, 781 <&pmx_core 69 82 1>, 782 <&pmx_core 70 81 1>, 783 <&pmx_core 71 80 1>, 784 <&pmx_core 72 70 1>, 785 <&pmx_core 73 78 1>, 786 <&pmx_core 74 77 1>, 787 <&pmx_core 75 76 1>, 788 <&pmx_core 76 75 1>, 789 <&pmx_core 77 74 1>, 790 <&pmx_core 78 73 1>, 791 <&pmx_core 79 72 1>, 792 <&pmx_core 80 103 1>, 793 <&pmx_core 81 102 1>, 794 <&pmx_core 82 101 1>, 795 <&pmx_core 83 100 1>, 796 <&pmx_core 84 99 1>, 797 <&pmx_core 85 98 1>, 798 <&pmx_core 86 97 1>, 799 <&pmx_core 87 96 1>, 800 <&pmx_core 88 95 1>, 801 <&pmx_core 89 94 1>, 802 <&pmx_core 90 93 1>, 803 <&pmx_core 91 92 1>, 804 <&pmx_core 92 91 1>, 805 <&pmx_core 93 90 1>, 806 <&pmx_core 94 89 1>, 807 <&pmx_core 95 88 1>, 808 <&pmx_core 96 158 1>, 809 <&pmx_core 97 157 1>, 810 <&pmx_core 98 156 1>, 811 <&pmx_core 99 155 1>, 812 <&pmx_core 100 154 1>, 813 <&pmx_core 101 129 1>, 814 <&pmx_core 102 113 1>, 815 <&pmx_core 103 112 1>, 816 <&pmx_core 104 111 1>, 817 <&pmx_core 105 110 1>, 818 <&pmx_core 106 109 1>, 819 <&pmx_core 107 108 1>, 820 <&pmx_core 108 107 1>, 821 <&pmx_core 109 106 1>, 822 <&pmx_core 110 105 1>, 823 <&pmx_core 111 104 1>, 824 <&pmx_core 112 145 1>, 825 <&pmx_core 113 144 1>, 826 <&pmx_core 114 143 1>, 827 <&pmx_core 115 142 1>, 828 <&pmx_core 116 141 1>, 829 <&pmx_core 117 140 1>, 830 <&pmx_core 118 139 1>, 831 <&pmx_core 119 138 1>, 832 <&pmx_core 120 137 1>, 833 <&pmx_core 121 136 1>, 834 <&pmx_core 122 135 1>, 835 <&pmx_core 123 134 1>, 836 <&pmx_core 124 133 1>, 837 <&pmx_core 125 132 1>, 838 <&pmx_core 126 131 1>, 839 <&pmx_core 127 130 1>, 840 <&pmx_core 128 159 1>, 841 <&pmx_core 129 31 1>, 842 <&pmx_core 130 30 1>, 843 <&pmx_core 131 20 1>, 844 <&pmx_core 132 28 1>, 845 <&pmx_core 133 27 1>, 846 <&pmx_core 134 26 1>, 847 <&pmx_core 135 23 1>, 848 <&pmx_core 136 153 1>, 849 <&pmx_core 137 152 1>, 850 <&pmx_core 138 151 1>, 851 <&pmx_core 139 150 1>, 852 <&pmx_core 140 149 1>, 853 <&pmx_core 141 148 1>, 854 <&pmx_core 142 147 1>, 855 <&pmx_core 143 146 1>; 856 }; 857 psc1: clock-controller@227000 { 858 compatible = "ti,da850-psc1"; 859 reg = <0x227000 0x1000>; 860 #clock-cells = <1>; 861 #power-domain-cells = <1>; 862 clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, 863 <&async3_clk>; 864 clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; 865 assigned-clocks = <&async3_clk>; 866 assigned-clock-parents = <&pll1_sysclk 2>; 867 }; 868 pinconf: pin-controller@22c00c { 869 compatible = "ti,da850-pupd"; 870 reg = <0x22c00c 0x8>; 871 status = "disabled"; 872 }; 873 874 mcasp0: mcasp@100000 { 875 compatible = "ti,da830-mcasp-audio"; 876 reg = <0x100000 0x2000>, 877 <0x102000 0x400000>; 878 reg-names = "mpu", "dat"; 879 interrupts = <54>; 880 interrupt-names = "common"; 881 power-domains = <&psc1 7>; 882 status = "disabled"; 883 dmas = <&edma0 1 1>, 884 <&edma0 0 1>; 885 dma-names = "tx", "rx"; 886 }; 887 888 lcdc: display@213000 { 889 compatible = "ti,da850-tilcdc"; 890 reg = <0x213000 0x1000>; 891 interrupts = <52>; 892 max-pixelclock = <37500>; 893 clocks = <&psc1 16>; 894 clock-names = "fck"; 895 power-domains = <&psc1 16>; 896 status = "disabled"; 897 }; 898 }; 899 aemif: aemif@68000000 { 900 compatible = "ti,da850-aemif"; 901 #address-cells = <2>; 902 #size-cells = <1>; 903 904 reg = <0x68000000 0x00008000>; 905 ranges = <0 0 0x60000000 0x08000000 906 1 0 0x68000000 0x00008000>; 907 clocks = <&psc0 3>; 908 clock-names = "aemif"; 909 clock-ranges; 910 status = "disabled"; 911 }; 912 memctrl: memory-controller@b0000000 { 913 compatible = "ti,da850-ddr-controller"; 914 reg = <0xb0000000 0xe8>; 915 status = "disabled"; 916 }; 917}; 918