1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP Mini Configuration
4 *
5 * (C) Copyright 2015 - 2020, Xilinx, Inc.
6 *
7 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13/ {
14	model = "ZynqMP MINI QSPI";
15	compatible = "xlnx,zynqmp";
16	#address-cells = <2>;
17	#size-cells = <1>;
18
19	aliases {
20		serial0 = &dcc;
21		spi0 = &qspi;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@fffc0000 {
29		device_type = "memory";
30		reg = <0x0 0xfffc0000 0x40000>;
31	};
32
33	dcc: dcc {
34		compatible = "arm,dcc";
35		status = "disabled";
36		bootph-all;
37	};
38
39	misc_clk: misc-clk {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <125000000>;
43	};
44
45	qspi: spi@ff0f0000 {
46		compatible = "xlnx,zynqmp-qspi-1.0";
47		status = "disabled";
48		clock-names = "ref_clk", "pclk";
49		clocks = <&misc_clk &misc_clk>;
50		num-cs = <1>;
51		reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
52		#address-cells = <1>;
53		#size-cells = <0>;
54	};
55};
56
57&qspi {
58	status = "okay";
59	flash0: flash@0 {
60		compatible = "jedec,spi-nor";
61		#address-cells = <1>;
62		#size-cells = <1>;
63		reg = <0x0>;
64		spi-tx-bus-width = <4>;
65		spi-rx-bus-width = <4>;
66		spi-max-frequency = <40000000>;
67	};
68};
69
70&dcc {
71	status = "okay";
72};
73