1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015-2019 Toradex, Inc.
4 *
5 * Based on vf610twr.c:
6 * Copyright 2013 Freescale Semiconductor, Inc.
7 */
8
9 #include <init.h>
10 #include <asm/global_data.h>
11
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/ddrmc-vf610.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/iomux-vf610.h>
17 #include <asm/gpio.h>
18 #include <asm/io.h>
19 #include <env.h>
20 #include <fdt_support.h>
21 #include <g_dnl.h>
22 #include <jffs2/load_kernel.h>
23 #include <mtd_node.h>
24 #include <usb.h>
25
26 #include "../common/tdx-common.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define PTC0_GPIO_45 45
31
32 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
33 { DDRMC_CR79_CTLUPD_AREF(1), 79 },
34 /* sets manual values for read lvl. (gate) delay of data slice 0/1 */
35 { DDRMC_CR105_RDLVL_DL_0(28), 105 },
36 { DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
37 { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
38 { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
39
40 /* AXI */
41 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
42 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
43 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
44 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
45 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
46 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
47 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
48 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
49 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
50 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
51 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
52 { DDRMC_CR126_PHY_RDLAT(8), 126 },
53 { DDRMC_CR132_WRLAT_ADJ(5) |
54 DDRMC_CR132_RDLAT_ADJ(6), 132 },
55 { DDRMC_CR137_PHYCTL_DL(2), 137 },
56 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
57 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
58 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
59 DDRMC_CR139_PHY_WRLV_DLL(3) |
60 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
61 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
62 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
63 DDRMC_CR143_RDLV_MXDL(128), 143 },
64 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
65 DDRMC_CR144_PHY_RDLV_DLL(3) |
66 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
67 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
68 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
69 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
70 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
71 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
72 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
73
74 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
75 DDRMC_CR154_PAD_ZQ_MODE(1) |
76 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
77 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
78 { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
79 { DDRMC_CR158_TWR(6), 158 },
80 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
81 DDRMC_CR161_TODTH_WR(2), 161 },
82 /* end marker */
83 { 0, -1 }
84 };
85
dram_init(void)86 int dram_init(void)
87 {
88 static const struct ddr3_jedec_timings timings = {
89 .tinit = 5,
90 .trst_pwron = 80000,
91 .cke_inactive = 200000,
92 .wrlat = 5,
93 .caslat_lin = 12,
94 .trc = 21,
95 .trrd = 4,
96 .tccd = 4,
97 .tbst_int_interval = 0,
98 .tfaw = 20,
99 .trp = 6,
100 .twtr = 4,
101 .tras_min = 15,
102 .tmrd = 4,
103 .trtp = 4,
104 .tras_max = 28080,
105 .tmod = 12,
106 .tckesr = 4,
107 .tcke = 3,
108 .trcd_int = 6,
109 .tras_lockout = 0,
110 .tdal = 12,
111 .bstlen = 3,
112 .tdll = 512, /* not applicable since freq. scaling
113 * is not used
114 */
115 .trp_ab = 6,
116 .tref = 3120,
117 .trfc = 64,
118 .tref_int = 0,
119 .tpdex = 3,
120 .txpdll = 10,
121 .txsnr = 68, /* changed to conform to JEDEC
122 * specifications
123 */
124 .txsr = 506, /* changed to conform to JEDEC
125 * specifications
126 */
127 .cksrx = 5,
128 .cksre = 5,
129 .freq_chg_en = 0,
130 .zqcl = 256,
131 .zqinit = 512,
132 .zqcs = 64,
133 .ref_per_zq = 64,
134 .zqcs_rotate = 0,
135 .aprebit = 10,
136 .cmd_age_cnt = 64,
137 .age_cnt = 64,
138 .q_fullness = 7,
139 .odt_rd_mapcs0 = 0,
140 .odt_wr_mapcs0 = 1,
141 .wlmrd = 40,
142 .wldqsen = 25,
143 };
144
145 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
146 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
147
148 return 0;
149 }
150
151 #ifdef CONFIG_VYBRID_GPIO
setup_iomux_gpio(void)152 static void setup_iomux_gpio(void)
153 {
154 static const iomux_v3_cfg_t gpio_pads[] = {
155 VF610_PAD_PTA17__GPIO_7,
156 VF610_PAD_PTA20__GPIO_10,
157 VF610_PAD_PTA21__GPIO_11,
158 VF610_PAD_PTA30__GPIO_20,
159 VF610_PAD_PTA31__GPIO_21,
160 VF610_PAD_PTB0__GPIO_22,
161 VF610_PAD_PTB1__GPIO_23,
162 VF610_PAD_PTB6__GPIO_28,
163 VF610_PAD_PTB7__GPIO_29,
164 VF610_PAD_PTB8__GPIO_30,
165 VF610_PAD_PTB9__GPIO_31,
166 VF610_PAD_PTB12__GPIO_34,
167 VF610_PAD_PTB13__GPIO_35,
168 VF610_PAD_PTB16__GPIO_38,
169 VF610_PAD_PTB17__GPIO_39,
170 VF610_PAD_PTB18__GPIO_40,
171 VF610_PAD_PTB21__GPIO_43,
172 VF610_PAD_PTB22__GPIO_44,
173 VF610_PAD_PTC0__GPIO_45,
174 VF610_PAD_PTC1__GPIO_46,
175 VF610_PAD_PTC2__GPIO_47,
176 VF610_PAD_PTC3__GPIO_48,
177 VF610_PAD_PTC4__GPIO_49,
178 VF610_PAD_PTC5__GPIO_50,
179 VF610_PAD_PTC6__GPIO_51,
180 VF610_PAD_PTC7__GPIO_52,
181 VF610_PAD_PTC8__GPIO_53,
182 VF610_PAD_PTD31__GPIO_63,
183 VF610_PAD_PTD30__GPIO_64,
184 VF610_PAD_PTD29__GPIO_65,
185 VF610_PAD_PTD28__GPIO_66,
186 VF610_PAD_PTD27__GPIO_67,
187 VF610_PAD_PTD26__GPIO_68,
188 VF610_PAD_PTD25__GPIO_69,
189 VF610_PAD_PTD24__GPIO_70,
190 VF610_PAD_PTD9__GPIO_88,
191 VF610_PAD_PTD10__GPIO_89,
192 VF610_PAD_PTD11__GPIO_90,
193 VF610_PAD_PTD12__GPIO_91,
194 VF610_PAD_PTD13__GPIO_92,
195 VF610_PAD_PTB23__GPIO_93,
196 VF610_PAD_PTB26__GPIO_96,
197 VF610_PAD_PTB28__GPIO_98,
198 VF610_PAD_PTC30__GPIO_103,
199 VF610_PAD_PTA7__GPIO_134,
200 };
201
202 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
203 }
204 #endif
205
is_colibri_vf61(void)206 static inline int is_colibri_vf61(void)
207 {
208 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
209
210 /*
211 * Detect board type by Level 2 Cache: VF50 don't have any
212 * Level 2 Cache.
213 */
214 return !!mscm->cpxcfg1;
215 }
216
clock_init(void)217 static void clock_init(void)
218 {
219 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
220 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
221 u32 pfd_clk_sel, ddr_clk_sel;
222
223 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
224 CCM_CCGR0_UART0_CTRL_MASK);
225 #ifdef CONFIG_FSL_DSPI
226 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
227 #endif
228 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
229 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
230 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
231 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
232 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
233 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
234 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
235 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
236 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
237 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
238 CCM_CCGR4_GPC_CTRL_MASK);
239 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
240 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
241 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
242 CCM_CCGR7_SDHC1_CTRL_MASK);
243 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
244 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
245 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
246 CCM_CCGR10_NFC_CTRL_MASK);
247
248 #ifdef CONFIG_USB_EHCI_VF
249 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
250 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
251
252 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
253 ANADIG_PLL3_CTRL_POWERDOWN |
254 ANADIG_PLL3_CTRL_DIV_SELECT,
255 ANADIG_PLL3_CTRL_ENABLE);
256 clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
257 ANADIG_PLL7_CTRL_POWERDOWN |
258 ANADIG_PLL7_CTRL_DIV_SELECT,
259 ANADIG_PLL7_CTRL_ENABLE);
260 #endif
261
262 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
263 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
264 ANADIG_PLL5_CTRL_DIV_SELECT);
265
266 if (is_colibri_vf61()) {
267 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
268 ANADIG_PLL2_CTRL_POWERDOWN,
269 ANADIG_PLL2_CTRL_ENABLE |
270 ANADIG_PLL2_CTRL_DIV_SELECT);
271 }
272
273 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
274 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
275
276 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
277 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
278
279 /* See "Typical PLL Configuration" */
280 if (is_colibri_vf61()) {
281 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
282 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
283 } else {
284 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
285 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
286 }
287
288 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
289 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
290 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
291 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
292 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
293 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
294 CCM_CCSR_SYS_CLK_SEL(4));
295
296 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
297 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
298 CCM_CACRR_ARM_CLK_DIV(0));
299 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
300 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
301 CCM_CSCMR1_NFC_CLK_SEL(0));
302 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
303 CCM_CSCDR1_RMII_CLK_EN);
304 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
305 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
306 CCM_CSCDR2_NFC_EN);
307 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
308 CCM_CSCDR3_NFC_PRE_DIV(3));
309 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
310 CCM_CSCMR2_RMII_CLK_SEL(2));
311 }
312
mscm_init(void)313 static void mscm_init(void)
314 {
315 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
316 int i;
317
318 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
319 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
320 }
321
board_early_init_f(void)322 int board_early_init_f(void)
323 {
324 clock_init();
325 mscm_init();
326
327 #ifdef CONFIG_VYBRID_GPIO
328 setup_iomux_gpio();
329 #endif
330
331 return 0;
332 }
333
334 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)335 int board_late_init(void)
336 {
337 struct src *src = (struct src *)SRC_BASE_ADDR;
338
339 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
340 == SRC_SBMR2_BMOD_SERIAL) {
341 printf("Serial Downloader recovery mode, disable autoboot\n");
342 env_set("bootdelay", "-1");
343 }
344
345 return 0;
346 }
347 #endif /* CONFIG_BOARD_LATE_INIT */
348
board_init(void)349 int board_init(void)
350 {
351 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
352
353 /* address of boot parameters */
354 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
355
356 /*
357 * Enable external 32K Oscillator
358 *
359 * The internal clock experiences significant drift
360 * so we must use the external oscillator in order
361 * to maintain correct time in the hwclock
362 */
363 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
364
365 return 0;
366 }
367
368 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)369 int ft_board_setup(void *blob, struct bd_info *bd)
370 {
371 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
372 static const struct node_info nodes[] = {
373 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
374 };
375
376 /* Update partition nodes using info from mtdparts env var */
377 puts(" Updating MTD partitions...\n");
378 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
379 #endif
380
381 return ft_common_board_setup(blob, bd);
382 }
383 #endif
384
385 /*
386 * Backlight off before OS handover
387 */
board_preboot_os(void)388 void board_preboot_os(void)
389 {
390 gpio_request(PTC0_GPIO_45, "BL_ON");
391 gpio_direction_output(PTC0_GPIO_45, 0);
392 }
393