1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx AXI Bridge for PCI Express Driver
4 *
5 * Copyright (C) 2016 Imagination Technologies
6 */
7
8 #include <dm.h>
9 #include <pci.h>
10 #include <linux/bitops.h>
11 #include <linux/printk.h>
12 #include <linux/io.h>
13 #include <linux/err.h>
14
15 /**
16 * struct xilinx_pcie - Xilinx PCIe controller state
17 * @cfg_base: The base address of memory mapped configuration space
18 */
19 struct xilinx_pcie {
20 void *cfg_base;
21 pci_size_t size;
22 int first_busno;
23 };
24
25 /* Register definitions */
26 #define XILINX_PCIE_REG_BRIDGE_INFO 0x130
27 #define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_SHIFT 16
28 #define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_MASK (0x7 << 16)
29 #define XILINX_PCIE_REG_INT_MASK 0x13c
30 #define XILINX_PCIE_REG_PSCR 0x144
31 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
32 #define XILINX_PCIE_REG_RPSC 0x148
33 #define XILINX_PCIE_REG_RPSC_BEN BIT(0)
34 /**
35 * pcie_xilinx_link_up() - Check whether the PCIe link is up
36 * @pcie: Pointer to the PCI controller state
37 *
38 * Checks whether the PCIe link for the given device is up or down.
39 *
40 * Return: true if the link is up, else false
41 */
pcie_xilinx_link_up(struct xilinx_pcie * pcie)42 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
43 {
44 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
45
46 return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
47 }
48
49 /**
50 * pcie_xilinx_config_address() - Calculate the address of a config access
51 * @udev: Pointer to the PCI bus
52 * @bdf: Identifies the PCIe device to access
53 * @offset: The offset into the device's configuration space
54 * @paddress: Pointer to the pointer to write the calculates address to
55 *
56 * Calculates the address that should be accessed to perform a PCIe
57 * configuration space access for a given device identified by the PCIe
58 * controller device @pcie and the bus, device & function numbers in @bdf. If
59 * access to the device is not valid then the function will return an error
60 * code. Otherwise the address to access will be written to the pointer pointed
61 * to by @paddress.
62 *
63 * Return: 0 on success, else -ENODEV
64 */
pcie_xilinx_config_address(const struct udevice * udev,pci_dev_t bdf,uint offset,void ** paddress)65 static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
66 uint offset, void **paddress)
67 {
68 struct xilinx_pcie *pcie = dev_get_priv(udev);
69 unsigned int bus = PCI_BUS(bdf) - pcie->first_busno;
70 unsigned int dev = PCI_DEV(bdf);
71 unsigned int func = PCI_FUNC(bdf);
72 int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
73 void *addr;
74
75 if ((bus > 0) && !pcie_xilinx_link_up(pcie))
76 return -ENODEV;
77
78 if (bus > num_buses)
79 return -ENODEV;
80
81 /*
82 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
83 * limited to a single device each.
84 */
85 if ((bus < 2) && (dev > 0))
86 return -ENODEV;
87
88 addr = pcie->cfg_base;
89 addr += PCIE_ECAM_OFFSET(bus, dev, func, offset);
90 *paddress = addr;
91
92 return 0;
93 }
94
95 /**
96 * pcie_xilinx_read_config() - Read from configuration space
97 * @bus: Pointer to the PCI bus
98 * @bdf: Identifies the PCIe device to access
99 * @offset: The offset into the device's configuration space
100 * @valuep: A pointer at which to store the read value
101 * @size: Indicates the size of access to perform
102 *
103 * Read a value of size @size from offset @offset within the configuration
104 * space of the device identified by the bus, device & function numbers in @bdf
105 * on the PCI bus @bus.
106 *
107 * Return: 0 on success, else -ENODEV or -EINVAL
108 */
pcie_xilinx_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)109 static int pcie_xilinx_read_config(const struct udevice *bus, pci_dev_t bdf,
110 uint offset, ulong *valuep,
111 enum pci_size_t size)
112 {
113 return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
114 bdf, offset, valuep, size);
115 }
116
117 /**
118 * pcie_xilinx_write_config() - Write to configuration space
119 * @bus: Pointer to the PCI bus
120 * @bdf: Identifies the PCIe device to access
121 * @offset: The offset into the device's configuration space
122 * @value: The value to write
123 * @size: Indicates the size of access to perform
124 *
125 * Write the value @value of size @size from offset @offset within the
126 * configuration space of the device identified by the bus, device & function
127 * numbers in @bdf on the PCI bus @bus.
128 *
129 * Return: 0 on success, else -ENODEV or -EINVAL
130 */
pcie_xilinx_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)131 static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
132 uint offset, ulong value,
133 enum pci_size_t size)
134 {
135 return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
136 bdf, offset, value, size);
137 }
138
139 /**
140 * pcie_xilinx_of_to_plat() - Translate from DT to device state
141 * @dev: A pointer to the device being operated on
142 *
143 * Translate relevant data from the device tree pertaining to device @dev into
144 * state that the driver will later make use of. This state is stored in the
145 * device's private data structure.
146 *
147 * Return: 0 on success, else -EINVAL
148 */
pcie_xilinx_of_to_plat(struct udevice * dev)149 static int pcie_xilinx_of_to_plat(struct udevice *dev)
150 {
151 struct xilinx_pcie *pcie = dev_get_priv(dev);
152 fdt_addr_t addr;
153 fdt_size_t size;
154
155 addr = dev_read_addr_size(dev, &size);
156 if (addr == FDT_ADDR_T_NONE)
157 return -EINVAL;
158
159 pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE);
160 if (!pcie->cfg_base)
161 return -ENOMEM;
162 pcie->size = size;
163 return 0;
164 }
165
pci_xilinx_probe(struct udevice * dev)166 static int pci_xilinx_probe(struct udevice *dev)
167 {
168 struct xilinx_pcie *pcie = dev_get_priv(dev);
169 u32 rpsc;
170 int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
171
172 pcie->first_busno = dev_seq(dev);
173
174 /* Disable all interrupts */
175 writel(0, pcie->cfg_base + XILINX_PCIE_REG_INT_MASK);
176
177 /* Enable the bridge */
178 rpsc = readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
179 rpsc |= XILINX_PCIE_REG_RPSC_BEN;
180 writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
181
182 /* Enable access to all possible subordinate buses */
183 writel((0 << 0) | (1 << 8) | (num_buses << 16),
184 pcie->cfg_base + PCI_PRIMARY_BUS);
185
186 return 0;
187 }
188
189 static const struct dm_pci_ops pcie_xilinx_ops = {
190 .read_config = pcie_xilinx_read_config,
191 .write_config = pcie_xilinx_write_config,
192 };
193
194 static const struct udevice_id pcie_xilinx_ids[] = {
195 { .compatible = "xlnx,axi-pcie-host-1.00.a" },
196 { }
197 };
198
199 U_BOOT_DRIVER(pcie_xilinx) = {
200 .name = "pcie_xilinx",
201 .id = UCLASS_PCI,
202 .of_match = pcie_xilinx_ids,
203 .ops = &pcie_xilinx_ops,
204 .of_to_plat = pcie_xilinx_of_to_plat,
205 .probe = pci_xilinx_probe,
206 .priv_auto = sizeof(struct xilinx_pcie),
207 };
208