1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) Aspeed Technology Inc. 4 */ 5 #ifndef __ASM_AST2700_SDRAM_H__ 6 #define __ASM_AST2700_SDRAM_H__ 7 8 struct sdrammc_regs { 9 u32 prot_key; 10 u32 intr_status; 11 u32 intr_clear; 12 u32 intr_mask; 13 u32 mcfg; 14 u32 mctl; 15 u32 msts; 16 u32 error_status; 17 u32 actime1; 18 u32 actime2; 19 u32 actime3; 20 u32 actime4; 21 u32 actime5; 22 u32 actime6; 23 u32 actime7; 24 u32 dfi_timing; 25 u32 dcfg; 26 u32 dctl; 27 u32 mrctl; 28 u32 mrwr; 29 u32 mrrd; 30 u32 mr01; 31 u32 mr23; 32 u32 mr45; 33 u32 mr67; 34 u32 refctl; 35 u32 refmng_ctl; 36 u32 refsts; 37 u32 zqctl; 38 u32 ecc_addr_range; 39 u32 ecc_failure_status; 40 u32 ecc_failure_addr; 41 u32 ecc_test_control; 42 u32 ecc_test_status; 43 u32 arbctl; 44 u32 enccfg; 45 u32 protect_lock_set; 46 u32 protect_lock_status; 47 u32 protect_lock_reset; 48 u32 enc_min_addr; 49 u32 enc_max_addr; 50 u32 enc_key[4]; 51 u32 enc_iv[3]; 52 u32 bistcfg; 53 u32 bist_addr; 54 u32 bist_size; 55 u32 bist_patt; 56 u32 bist_res; 57 u32 bist_fail_addr; 58 u32 bist_fail_data[4]; 59 u32 reserved2[2]; 60 u32 debug_control; 61 u32 debug_status; 62 u32 phy_intf_status; 63 u32 testcfg; 64 u32 gfmcfg; 65 u32 gfm0ctl; 66 u32 gfm1ctl; 67 u32 reserved3[0xf8]; 68 }; 69 70 #define DRAMC_UNLK_KEY 0x1688a8a8 71 72 /* offset 0x04 */ 73 #define DRAMC_IRQSTA_PWRCTL_ERR BIT(16) 74 #define DRAMC_IRQSTA_PHY_ERR BIT(15) 75 #define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12) 76 #define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11) 77 #define DRAMC_IRQSTA_REF_DONE BIT(10) 78 #define DRAMC_IRQSTA_ZQ_DONE BIT(9) 79 #define DRAMC_IRQSTA_BIST_DONE BIT(8) 80 #define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5) 81 #define DRAMC_IRQSTA_ECC_ERR BIT(4) 82 #define DRAMC_IRQSTA_PROT_ERR BIT(3) 83 #define DRAMC_IRQSTA_OVERSZ_ERR BIT(2) 84 #define DRAMC_IRQSTA_MR_DONE BIT(1) 85 #define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0) 86 87 /* offset 0x14 */ 88 #define DRAMC_MCTL_WB_SOFT_RESET BIT(24) 89 #define DRAMC_MCTL_PHY_CLK_DIS BIT(18) 90 #define DRAMC_MCTL_PHY_RESET BIT(17) 91 #define DRAMC_MCTL_PHY_POWER_ON BIT(16) 92 #define DRAMC_MCTL_FREQ_CHG_START BIT(3) 93 #define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2) 94 #define DRAMC_MCTL_SELF_REF_START BIT(1) 95 #define DRAMC_MCTL_PHY_INIT_START BIT(0) 96 97 /* offset 0x40 */ 98 #define DRAMC_DFICFG_WD_POL BIT(18) 99 #define DRAMC_DFICFG_CKE_OUT BIT(17) 100 #define DRAMC_DFICFG_RESET BIT(16) 101 102 /* offset 0x48 */ 103 #define DRAMC_MRCTL_ERR_STATUS BIT(31) 104 #define DRAMC_MRCTL_READY_STATUS BIT(30) 105 #define DRAMC_MRCTL_MR_ADDR BIT(8) 106 #define DRAMC_MRCTL_CMD_DLL_RST BIT(7) 107 #define DRAMC_MRCTL_CMD_DQ_SEL BIT(6) 108 #define DRAMC_MRCTL_CMD_TYPE BIT(2) 109 #define DRAMC_MRCTL_CMD_WR_CTL BIT(1) 110 #define DRAMC_MRCTL_CMD_START BIT(0) 111 112 /* offset 0xC0 */ 113 #define DRAMC_BISTRES_RUNNING BIT(10) 114 #define DRAMC_BISTRES_FAIL BIT(9) 115 #define DRAMC_BISTRES_DONE BIT(8) 116 #define DRAMC_BISTCFG_INIT_MODE BIT(7) 117 #define DRAMC_BISTCFG_PMODE GENMASK(6, 4) 118 #define DRAMC_BISTCFG_BMODE GENMASK(3, 2) 119 #define DRAMC_BISTCFG_ENABLE BIT(1) 120 #define DRAMC_BISTCFG_START BIT(0) 121 #define BIST_PMODE_CRC (3) 122 #define BIST_BMODE_RW_SWITCH (3) 123 124 /* DRAMC048 MR Control Register */ 125 #define MR_TYPE_SHIFT 2 126 #define MR_RW (0 << MR_TYPE_SHIFT) 127 #define MR_MPC BIT(2) 128 #define MR_VREFCS (2 << MR_TYPE_SHIFT) 129 #define MR_VREFCA (3 << MR_TYPE_SHIFT) 130 #define MR_ADDRESS_SHIFT 8 131 #define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL) 132 #define MR_NUM_SHIFT 4 133 #define MR_NUM(n) ((n) << MR_NUM_SHIFT) 134 #define MR_DLL_RESET BIT(7) 135 #define MR_1T_MODE BIT(16) 136 137 #endif 138