1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2011 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * Aaron <leafy.myeh@allwinnertech.com> 6 * 7 * MMC register definition for allwinner sunxi platform. 8 */ 9 10 #ifndef _SUNXI_MMC_H 11 #define _SUNXI_MMC_H 12 13 #include <linux/types.h> 14 15 struct sunxi_mmc { 16 u32 gctrl; /* 0x00 global control */ 17 u32 clkcr; /* 0x04 clock control */ 18 u32 timeout; /* 0x08 time out */ 19 u32 width; /* 0x0c bus width */ 20 u32 blksz; /* 0x10 block size */ 21 u32 bytecnt; /* 0x14 byte count */ 22 u32 cmd; /* 0x18 command */ 23 u32 arg; /* 0x1c argument */ 24 u32 resp0; /* 0x20 response 0 */ 25 u32 resp1; /* 0x24 response 1 */ 26 u32 resp2; /* 0x28 response 2 */ 27 u32 resp3; /* 0x2c response 3 */ 28 u32 imask; /* 0x30 interrupt mask */ 29 u32 mint; /* 0x34 masked interrupt status */ 30 u32 rint; /* 0x38 raw interrupt status */ 31 u32 status; /* 0x3c status */ 32 u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ 33 u32 funcsel; /* 0x44 function select */ 34 u32 cbcr; /* 0x48 CIU byte count */ 35 u32 bbcr; /* 0x4c BIU byte count */ 36 u32 dbgc; /* 0x50 debug enable */ 37 u32 res0; /* 0x54 reserved */ 38 u32 a12a; /* 0x58 Auto command 12 argument */ 39 u32 ntsr; /* 0x5c New timing set register */ 40 u32 res1[6]; 41 u32 hwrst; /* 0x78 Hardware Reset */ 42 u32 res5; 43 u32 dmac; /* 0x80 internal DMA control */ 44 u32 dlba; /* 0x84 internal DMA descr list base address */ 45 u32 idst; /* 0x88 internal DMA status */ 46 u32 idie; /* 0x8c internal DMA interrupt enable */ 47 u32 chda; /* 0x90 */ 48 u32 cbda; /* 0x94 */ 49 u32 res2[26]; 50 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) 51 u32 thldc; /* 0x100 Threshold control */ 52 u32 res3[16]; 53 u32 samp_dl; 54 u32 res4[46]; 55 #endif 56 u32 fifo; /* 0x100 / 0x200 FIFO access address */ 57 }; 58 59 #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) 60 #define SUNXI_MMC_CLK_ENABLE (0x1 << 16) 61 #define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) 62 63 #define SUNXI_MMC_GCTRL 0x000 64 #define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) 65 #define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) 66 #define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) 67 #define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ 68 SUNXI_MMC_GCTRL_FIFO_RESET|\ 69 SUNXI_MMC_GCTRL_DMA_RESET) 70 #define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) 71 #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) 72 73 #define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) 74 #define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) 75 #define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) 76 #define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) 77 #define SUNXI_MMC_CMD_WRITE (0x1 << 10) 78 #define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) 79 #define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) 80 #define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) 81 #define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) 82 #define SUNXI_MMC_CMD_START (0x1 << 31) 83 84 #define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) 85 #define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) 86 #define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) 87 #define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) 88 #define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) 89 #define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) 90 #define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) 91 #define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) 92 #define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) 93 #define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) 94 #define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) 95 #define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) 96 #define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) 97 #define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) 98 #define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) 99 #define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) 100 #define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) 101 #define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) 102 #define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ 103 (SUNXI_MMC_RINT_RESP_ERROR | \ 104 SUNXI_MMC_RINT_RESP_CRC_ERROR | \ 105 SUNXI_MMC_RINT_DATA_CRC_ERROR | \ 106 SUNXI_MMC_RINT_RESP_TIMEOUT | \ 107 SUNXI_MMC_RINT_DATA_TIMEOUT | \ 108 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ 109 SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ 110 SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ 111 SUNXI_MMC_RINT_START_BIT_ERROR | \ 112 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ 113 #define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ 114 (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ 115 SUNXI_MMC_RINT_DATA_OVER | \ 116 SUNXI_MMC_RINT_COMMAND_DONE | \ 117 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) 118 119 #define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) 120 #define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) 121 #define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) 122 #define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) 123 #define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) 124 #define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) 125 #define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) 126 #define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff) 127 128 #define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) 129 130 #define SUNXI_MMC_HWRST 0x078 131 #define SUNXI_MMC_HWRST_ASSERT (0x0 << 0) 132 #define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0) 133 134 #define SUNXI_MMC_IDMAC_RESET (0x1 << 0) 135 #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) 136 #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) 137 138 #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) 139 #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) 140 141 #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) 142 #define SUNXI_MMC_COMMON_RESET (1 << 18) 143 144 #define SUNXI_MMC_THLDC 0x100 145 #define SUNXI_MMC_THLDC_READ_EN (0x1 << 0) 146 #define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1) 147 #define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2) 148 #define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16) 149 150 #define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) 151 152 #endif /* _SUNXI_MMC_H */ 153