1 /* 2 * MPC8xx Internal Memory Map 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * The I/O on the MPC860 is comprised of blocks of special registers 6 * and the dual port ram for the Communication Processor Module. 7 * Within this space are functional units such as the SIU, memory 8 * controller, system timers, and other control functions. It is 9 * a combination that I found difficult to separate into logical 10 * functional files.....but anyone else is welcome to try. -- Dan 11 */ 12 #ifndef __IMMAP_8XX__ 13 #define __IMMAP_8XX__ 14 15 #include <linux/types.h> 16 17 /* System configuration registers. 18 */ 19 typedef struct sys_conf { 20 uint sc_siumcr; 21 uint sc_sypcr; 22 uint sc_swt; 23 char res1[2]; 24 ushort sc_swsr; 25 uint sc_sipend; 26 uint sc_simask; 27 uint sc_siel; 28 uint sc_sivec; 29 uint sc_tesr; 30 char res2[0xc]; 31 uint sc_sdcr; 32 char res3[0x4c]; 33 } sysconf8xx_t; 34 35 /* PCMCIA configuration registers. 36 */ 37 typedef struct pcmcia_conf { 38 uint pcmc_pbr0; 39 uint pcmc_por0; 40 uint pcmc_pbr1; 41 uint pcmc_por1; 42 uint pcmc_pbr2; 43 uint pcmc_por2; 44 uint pcmc_pbr3; 45 uint pcmc_por3; 46 uint pcmc_pbr4; 47 uint pcmc_por4; 48 uint pcmc_pbr5; 49 uint pcmc_por5; 50 uint pcmc_pbr6; 51 uint pcmc_por6; 52 uint pcmc_pbr7; 53 uint pcmc_por7; 54 char res1[0x20]; 55 uint pcmc_pgcra; 56 uint pcmc_pgcrb; 57 uint pcmc_pscr; 58 char res2[4]; 59 uint pcmc_pipr; 60 char res3[4]; 61 uint pcmc_per; 62 char res4[4]; 63 } pcmconf8xx_t; 64 65 /* Memory controller registers. 66 */ 67 typedef struct mem_ctlr { 68 uint memc_br0; 69 uint memc_or0; 70 uint memc_br1; 71 uint memc_or1; 72 uint memc_br2; 73 uint memc_or2; 74 uint memc_br3; 75 uint memc_or3; 76 uint memc_br4; 77 uint memc_or4; 78 uint memc_br5; 79 uint memc_or5; 80 uint memc_br6; 81 uint memc_or6; 82 uint memc_br7; 83 uint memc_or7; 84 char res1[0x24]; 85 uint memc_mar; 86 uint memc_mcr; 87 char res2[4]; 88 uint memc_mamr; 89 uint memc_mbmr; 90 ushort memc_mstat; 91 ushort memc_mptpr; 92 uint memc_mdr; 93 char res3[0x80]; 94 } memctl8xx_t; 95 96 /* System Integration Timers. 97 */ 98 typedef struct sys_int_timers { 99 ushort sit_tbscr; 100 char res0[0x02]; 101 uint sit_tbreff0; 102 uint sit_tbreff1; 103 char res1[0x14]; 104 ushort sit_rtcsc; 105 char res2[0x02]; 106 uint sit_rtc; 107 uint sit_rtsec; 108 uint sit_rtcal; 109 char res3[0x10]; 110 ushort sit_piscr; 111 char res4[2]; 112 uint sit_pitc; 113 uint sit_pitr; 114 char res5[0x34]; 115 } sit8xx_t; 116 117 #define TBSCR_TBIRQ_MASK ((ushort)0xff00) 118 #define TBSCR_REFA ((ushort)0x0080) 119 #define TBSCR_REFB ((ushort)0x0040) 120 #define TBSCR_REFAE ((ushort)0x0008) 121 #define TBSCR_REFBE ((ushort)0x0004) 122 #define TBSCR_TBF ((ushort)0x0002) 123 #define TBSCR_TBE ((ushort)0x0001) 124 125 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00) 126 #define RTCSC_SEC ((ushort)0x0080) 127 #define RTCSC_ALR ((ushort)0x0040) 128 #define RTCSC_38K ((ushort)0x0010) 129 #define RTCSC_SIE ((ushort)0x0008) 130 #define RTCSC_ALE ((ushort)0x0004) 131 #define RTCSC_RTF ((ushort)0x0002) 132 #define RTCSC_RTE ((ushort)0x0001) 133 134 #define PISCR_PIRQ_MASK ((ushort)0xff00) 135 #define PISCR_PS ((ushort)0x0080) 136 #define PISCR_PIE ((ushort)0x0004) 137 #define PISCR_PTF ((ushort)0x0002) 138 #define PISCR_PTE ((ushort)0x0001) 139 140 /* Clocks and Reset. 141 */ 142 typedef struct clk_and_reset { 143 uint car_sccr; 144 uint car_plprcr; 145 uint car_rsr; 146 char res[0x74]; /* Reserved area */ 147 } car8xx_t; 148 149 /* System Integration Timers keys. 150 */ 151 typedef struct sitk { 152 uint sitk_tbscrk; 153 uint sitk_tbreff0k; 154 uint sitk_tbreff1k; 155 uint sitk_tbk; 156 char res1[0x10]; 157 uint sitk_rtcsck; 158 uint sitk_rtck; 159 uint sitk_rtseck; 160 uint sitk_rtcalk; 161 char res2[0x10]; 162 uint sitk_piscrk; 163 uint sitk_pitck; 164 char res3[0x38]; 165 } sitk8xx_t; 166 167 /* Clocks and reset keys. 168 */ 169 typedef struct cark { 170 uint cark_sccrk; 171 uint cark_plprcrk; 172 uint cark_rsrk; 173 char res[0x474]; 174 } cark8xx_t; 175 176 /* The key to unlock registers maintained by keep-alive power. 177 */ 178 #define KAPWR_KEY ((unsigned int)0x55ccaa33) 179 180 /* I2C 181 */ 182 typedef struct i2c { 183 u_char i2c_i2mod; 184 char res1[3]; 185 u_char i2c_i2add; 186 char res2[3]; 187 u_char i2c_i2brg; 188 char res3[3]; 189 u_char i2c_i2com; 190 char res4[3]; 191 u_char i2c_i2cer; 192 char res5[3]; 193 u_char i2c_i2cmr; 194 char res6[0x8b]; 195 } i2c8xx_t; 196 197 /* DMA control/status registers. 198 */ 199 typedef struct sdma_csr { 200 char res1[4]; 201 uint sdma_sdar; 202 u_char sdma_sdsr; 203 char res3[3]; 204 u_char sdma_sdmr; 205 char res4[3]; 206 u_char sdma_idsr1; 207 char res5[3]; 208 u_char sdma_idmr1; 209 char res6[3]; 210 u_char sdma_idsr2; 211 char res7[3]; 212 u_char sdma_idmr2; 213 char res8[0x13]; 214 } sdma8xx_t; 215 216 /* Communication Processor Module Interrupt Controller. 217 */ 218 typedef struct cpm_ic { 219 ushort cpic_civr; 220 char res[0xe]; 221 uint cpic_cicr; 222 uint cpic_cipr; 223 uint cpic_cimr; 224 uint cpic_cisr; 225 } cpic8xx_t; 226 227 /* Input/Output Port control/status registers. 228 */ 229 typedef struct io_port { 230 ushort iop_padir; 231 ushort iop_papar; 232 ushort iop_paodr; 233 ushort iop_padat; 234 char res1[8]; 235 ushort iop_pcdir; 236 ushort iop_pcpar; 237 ushort iop_pcso; 238 ushort iop_pcdat; 239 ushort iop_pcint; 240 char res2[6]; 241 ushort iop_pddir; 242 ushort iop_pdpar; 243 char res3[2]; 244 ushort iop_pddat; 245 uint utmode; 246 char res4[4]; 247 } iop8xx_t; 248 249 /* Communication Processor Module Timers 250 */ 251 typedef struct cpm_timers { 252 ushort cpmt_tgcr; 253 char res1[0xe]; 254 ushort cpmt_tmr1; 255 ushort cpmt_tmr2; 256 ushort cpmt_trr1; 257 ushort cpmt_trr2; 258 ushort cpmt_tcr1; 259 ushort cpmt_tcr2; 260 ushort cpmt_tcn1; 261 ushort cpmt_tcn2; 262 ushort cpmt_tmr3; 263 ushort cpmt_tmr4; 264 ushort cpmt_trr3; 265 ushort cpmt_trr4; 266 ushort cpmt_tcr3; 267 ushort cpmt_tcr4; 268 ushort cpmt_tcn3; 269 ushort cpmt_tcn4; 270 ushort cpmt_ter1; 271 ushort cpmt_ter2; 272 ushort cpmt_ter3; 273 ushort cpmt_ter4; 274 char res2[8]; 275 } cpmtimer8xx_t; 276 277 /* Finally, the Communication Processor stuff..... 278 */ 279 typedef struct scc { /* Serial communication channels */ 280 uint scc_gsmrl; 281 uint scc_gsmrh; 282 ushort scc_psmr; 283 char res1[2]; 284 ushort scc_todr; 285 ushort scc_dsr; 286 ushort scc_scce; 287 char res2[2]; 288 ushort scc_sccm; 289 char res3; 290 u_char scc_sccs; 291 char res4[8]; 292 } scc_t; 293 294 typedef struct smc { /* Serial management channels */ 295 char res1[2]; 296 ushort smc_smcmr; 297 char res2[2]; 298 u_char smc_smce; 299 char res3[3]; 300 u_char smc_smcm; 301 char res4[5]; 302 } smc_t; 303 304 /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but 305 * it fits within the address space. 306 */ 307 308 typedef struct fec { 309 uint fec_addr_low; /* lower 32 bits of station address */ 310 ushort fec_addr_high; /* upper 16 bits of station address */ 311 ushort res1; /* reserved */ 312 uint fec_hash_table_high; /* upper 32-bits of hash table */ 313 uint fec_hash_table_low; /* lower 32-bits of hash table */ 314 uint fec_r_des_start; /* beginning of Rx descriptor ring */ 315 uint fec_x_des_start; /* beginning of Tx descriptor ring */ 316 uint fec_r_buff_size; /* Rx buffer size */ 317 uint res2[9]; /* reserved */ 318 uint fec_ecntrl; /* ethernet control register */ 319 uint fec_ievent; /* interrupt event register */ 320 uint fec_imask; /* interrupt mask register */ 321 uint fec_ivec; /* interrupt level and vector status */ 322 uint fec_r_des_active; /* Rx ring updated flag */ 323 uint fec_x_des_active; /* Tx ring updated flag */ 324 uint res3[10]; /* reserved */ 325 uint fec_mii_data; /* MII data register */ 326 uint fec_mii_speed; /* MII speed control register */ 327 uint res4[17]; /* reserved */ 328 uint fec_r_bound; /* end of RAM (read-only) */ 329 uint fec_r_fstart; /* Rx FIFO start address */ 330 uint res5[6]; /* reserved */ 331 uint fec_x_fstart; /* Tx FIFO start address */ 332 uint res6[17]; /* reserved */ 333 uint fec_fun_code; /* fec SDMA function code */ 334 uint res7[3]; /* reserved */ 335 uint fec_r_cntrl; /* Rx control register */ 336 uint fec_r_hash; /* Rx hash register */ 337 uint res8[14]; /* reserved */ 338 uint fec_x_cntrl; /* Tx control register */ 339 uint res9[0x1e]; /* reserved */ 340 } fec_t; 341 342 typedef struct comm_proc { 343 /* General control and status registers. 344 */ 345 ushort cp_cpcr; 346 u_char res1[2]; 347 ushort cp_rccr; 348 u_char res2; 349 u_char cp_rmds; 350 u_char res3[4]; 351 ushort cp_cpmcr1; 352 ushort cp_cpmcr2; 353 ushort cp_cpmcr3; 354 ushort cp_cpmcr4; 355 u_char res4[2]; 356 ushort cp_rter; 357 u_char res5[2]; 358 ushort cp_rtmr; 359 u_char res6[0x14]; 360 361 /* Baud rate generators. 362 */ 363 uint cp_brgc1; 364 uint cp_brgc2; 365 uint cp_brgc3; 366 uint cp_brgc4; 367 368 /* Serial Communication Channels. 369 */ 370 scc_t cp_scc[4]; 371 372 /* Serial Management Channels. 373 */ 374 smc_t cp_smc[2]; 375 376 /* Serial Peripheral Interface. 377 */ 378 ushort cp_spmode; 379 u_char res7[4]; 380 u_char cp_spie; 381 u_char res8[3]; 382 u_char cp_spim; 383 u_char res9[2]; 384 u_char cp_spcom; 385 u_char res10[2]; 386 387 /* Parallel Interface Port. 388 */ 389 u_char res11[2]; 390 ushort cp_pipc; 391 u_char res12[2]; 392 ushort cp_ptpr; 393 uint cp_pbdir; 394 uint cp_pbpar; 395 u_char res13[2]; 396 ushort cp_pbodr; 397 uint cp_pbdat; 398 399 /* Port E - MPC87x/88x only. 400 */ 401 uint cp_pedir; 402 uint cp_pepar; 403 uint cp_peso; 404 uint cp_peodr; 405 uint cp_pedat; 406 407 /* Communications Processor Timing Register - 408 Contains RMII Timing for the FECs on MPC87x/88x only. 409 */ 410 uint cp_cptr; 411 412 /* Serial Interface and Time Slot Assignment. 413 */ 414 uint cp_simode; 415 u_char cp_sigmr; 416 u_char res15; 417 u_char cp_sistr; 418 u_char cp_sicmr; 419 u_char res16[4]; 420 uint cp_sicr; 421 uint cp_sirp; 422 u_char res17[0xc]; 423 424 u_char res19[0x100]; 425 u_char cp_siram[0x200]; 426 427 /* The fast ethernet controller is not really part of the CPM, 428 * but it resides in the address space. 429 */ 430 fec_t cp_fec; 431 char res18[0xE00]; 432 433 /* The MPC885 family has a second FEC here */ 434 fec_t cp_fec2; 435 #define cp_fec1 cp_fec /* consistency macro */ 436 437 /* Dual Ported RAM follows. 438 * There are many different formats for this memory area 439 * depending upon the devices used and options chosen. 440 * Some processors don't have all of it populated. 441 */ 442 u_char cp_dpmem[0x2000]; /* BD / Data / ucode / Param RAM */ 443 } cpm8xx_t; 444 445 /* Internal memory map. 446 */ 447 typedef struct immap { 448 sysconf8xx_t im_siu_conf; /* SIU Configuration */ 449 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ 450 memctl8xx_t im_memctl; /* Memory Controller */ 451 sit8xx_t im_sit; /* System integration timers */ 452 car8xx_t im_clkrst; /* Clocks and reset */ 453 sitk8xx_t im_sitk; /* Sys int timer keys */ 454 cark8xx_t im_clkrstk; /* Clocks and reset keys */ 455 char res[96]; 456 i2c8xx_t im_i2c; /* I2C control/status */ 457 sdma8xx_t im_sdma; /* SDMA control/status */ 458 cpic8xx_t im_cpic; /* CPM Interrupt Controller */ 459 iop8xx_t im_ioport; /* IO Port control/status */ 460 cpmtimer8xx_t im_cpmtimer; /* CPM timers */ 461 cpm8xx_t im_cpm; /* Communication processor */ 462 } immap_t; 463 464 #endif /* __IMMAP_8XX__ */ 465