1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2003 Motorola Inc.
6 * Modified by Xianghua Xiao, X.Xiao@motorola.com
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 */
11
12 #include <display_options.h>
13 #include <env.h>
14 #include <init.h>
15 #include <net.h>
16 #include <watchdog.h>
17 #include <asm/processor.h>
18 #include <ioports.h>
19 #include <sata.h>
20 #include <fm_eth.h>
21 #include <asm/io.h>
22 #include <asm/cache.h>
23 #include <asm/mmu.h>
24 #include <fsl_errata.h>
25 #include <asm/fsl_law.h>
26 #include <asm/fsl_serdes.h>
27 #include <asm/fsl_srio.h>
28 #ifdef CONFIG_FSL_CORENET
29 #include <asm/fsl_portals.h>
30 #include <asm/fsl_liodn.h>
31 #include <fsl_qbman.h>
32 #endif
33 #include <fsl_usb.h>
34 #include <hwconfig.h>
35 #include <linux/compiler.h>
36 #include <linux/delay.h>
37 #include "mp.h"
38 #ifdef CONFIG_CHAIN_OF_TRUST
39 #include <fsl_validate.h>
40 #endif
41 #ifdef CONFIG_FSL_CAAM
42 #include <fsl_sec.h>
43 #endif
44 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
45 #include <asm/fsl_pamu.h>
46 #include <fsl_secboot_err.h>
47 #endif
48 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #include <nand.h>
50 #include <errno.h>
51 #endif
52 #ifndef CONFIG_ARCH_QEMU_E500
53 #include <fsl_ddr.h>
54 #endif
55 #include "../../../../drivers/ata/fsl_sata.h"
56 #ifdef CONFIG_U_QE
57 #include <fsl_qe.h>
58 #endif
59 #include <dm.h>
60
61 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
62 /*
63 * For deriving usb clock from 100MHz sysclk, reference divisor is set
64 * to a value of 5, which gives an intermediate value 20(100/5). The
65 * multiplication factor integer is set to 24, which when multiplied to
66 * above intermediate value provides clock for usb ip.
67 */
usb_single_source_clk_configure(struct ccsr_usb_phy * usb_phy)68 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
69 {
70 sys_info_t sysinfo;
71
72 get_sys_info(&sysinfo);
73 if (sysinfo.diff_sysclk == 1) {
74 clrbits_be32(&usb_phy->pllprg[1],
75 CFG_SYS_FSL_USB_PLLPRG2_MFI);
76 setbits_be32(&usb_phy->pllprg[1],
77 CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
78 CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
79 CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
80 }
81 }
82 #endif
83
84 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem * usb_phy)85 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
86 {
87 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
88 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
89
90 /* Increase Disconnect Threshold by 50mV */
91 xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
92 INC_DCNT_THRESHOLD_50MV;
93 /* Enable programming of USB High speed Disconnect threshold */
94 xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
95 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
96
97 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
98 /* Increase Disconnect Threshold by 50mV */
99 xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
100 INC_DCNT_THRESHOLD_50MV;
101 /* Enable programming of USB High speed Disconnect threshold */
102 xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
103 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
104 #else
105
106 u32 temp = 0;
107 u32 status = in_be32(&usb_phy->status1);
108
109 u32 squelch_prog_rd_0_2 =
110 (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
111 & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
112
113 u32 squelch_prog_rd_3_5 =
114 (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
115 & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
116
117 setbits_be32(&usb_phy->config1,
118 CFG_SYS_FSL_USB_HS_DISCNCT_INC);
119 setbits_be32(&usb_phy->config2,
120 CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
121
122 temp = squelch_prog_rd_0_2 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
123 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
124
125 temp = squelch_prog_rd_3_5 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
126 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
127 #endif
128 }
129 #endif
130
131 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
132 extern qe_iop_conf_t qe_iop_conf_tab[];
133 extern void qe_config_iopin(u8 port, u8 pin, int dir,
134 int open_drain, int assign);
135 extern void qe_init(uint qe_base);
136 extern void qe_reset(void);
137
config_qe_ioports(void)138 static void config_qe_ioports(void)
139 {
140 u8 port, pin;
141 int dir, open_drain, assign;
142 int i;
143
144 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
145 port = qe_iop_conf_tab[i].port;
146 pin = qe_iop_conf_tab[i].pin;
147 dir = qe_iop_conf_tab[i].dir;
148 open_drain = qe_iop_conf_tab[i].open_drain;
149 assign = qe_iop_conf_tab[i].assign;
150 qe_config_iopin(port, pin, dir, open_drain, assign);
151 }
152 }
153 #endif
154
155 #ifdef CONFIG_SYS_FSL_CPC
156 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram(void)157 void disable_cpc_sram(void)
158 {
159 int i;
160
161 cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
162
163 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
164 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
165 /* find and disable LAW of SRAM */
166 struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
167
168 if (law.index == -1) {
169 printf("\nFatal error happened\n");
170 return;
171 }
172 disable_law(law.index);
173
174 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
175 out_be32(&cpc->cpccsr0, 0);
176 out_be32(&cpc->cpcsrcr0, 0);
177 }
178 }
179 }
180 #endif
181
182 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
183 #ifdef CONFIG_POST
184 #error POST memory test cannot be enabled with TDM
185 #endif
enable_tdm_law(void)186 static void enable_tdm_law(void)
187 {
188 int ret;
189 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
190 int tdm_hwconfig_enabled = 0;
191
192 /*
193 * Extract hwconfig from environment since environment
194 * is not setup properly yet. Search for tdm entry in
195 * hwconfig.
196 */
197 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
198 if (ret > 0) {
199 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
200 /* If tdm is defined in hwconfig, set law for tdm workaround */
201 if (tdm_hwconfig_enabled)
202 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
203 LAW_TRGT_IF_CCSR);
204 }
205 }
206 #endif
207
enable_cpc(void)208 void enable_cpc(void)
209 {
210 int i;
211 int ret;
212 u32 size = 0;
213 u32 cpccfg0;
214 char buffer[HWCONFIG_BUFFER_SIZE];
215 char cpc_subarg[16];
216 bool have_hwconfig = false;
217 int cpc_args = 0;
218 cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
219
220 /* Extract hwconfig from environment */
221 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
222 if (ret > 0) {
223 /*
224 * If "en_cpc" is not defined in hwconfig then by default all
225 * cpcs are enable. If this config is defined then individual
226 * cpcs which have to be enabled should also be defined.
227 * e.g en_cpc:cpc1,cpc2;
228 */
229 if (hwconfig_f("en_cpc", buffer))
230 have_hwconfig = true;
231 }
232
233 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
234 if (have_hwconfig) {
235 sprintf(cpc_subarg, "cpc%u", i + 1);
236 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
237 if (cpc_args == 0)
238 continue;
239 }
240 cpccfg0 = in_be32(&cpc->cpccfg0);
241 size += CPC_CFG0_SZ_K(cpccfg0);
242
243 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
244 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
245 #endif
246 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
247 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
248 #endif
249 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
250 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
251 #endif
252 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
253 if (has_erratum_a006379()) {
254 setbits_be32(&cpc->cpchdbcr0,
255 CPC_HDBCR0_SPLRU_LEVEL_EN);
256 }
257 #endif
258
259 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
260 /* Read back to sync write */
261 in_be32(&cpc->cpccsr0);
262
263 }
264
265 puts("Corenet Platform Cache: ");
266 print_size(size * 1024, " enabled\n");
267 }
268
invalidate_cpc(void)269 static void invalidate_cpc(void)
270 {
271 int i;
272 cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
273
274 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
275 /* skip CPC when it used as all SRAM */
276 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
277 continue;
278 /* Flash invalidate the CPC and clear all the locks */
279 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
280 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
281 ;
282 }
283 }
284 #else
285 #define enable_cpc()
286 #define invalidate_cpc()
287 #define disable_cpc_sram()
288 #endif /* CONFIG_SYS_FSL_CPC */
289
290 /*
291 * Breathe some life into the CPU...
292 *
293 * Set up the memory map
294 * initialize a bunch of registers
295 */
296
297 #ifdef CONFIG_FSL_CORENET
corenet_tb_init(void)298 static void corenet_tb_init(void)
299 {
300 volatile ccsr_rcpm_t *rcpm =
301 (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
302 volatile ccsr_pic_t *pic =
303 (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
304 u32 whoami = in_be32(&pic->whoami);
305
306 /* Enable the timebase register for this core */
307 out_be32(&rcpm->ctbenrl, (1 << whoami));
308 }
309 #endif
310
311 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround(void)312 void fsl_erratum_a007212_workaround(void)
313 {
314 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
315 u32 ddr_pll_ratio;
316 u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
317 u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
318 u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
319 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
320 u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
321 u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
322 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
323 u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
324 u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
325 #endif
326 #endif
327 /*
328 * Even this workaround applies to selected version of SoCs, it is
329 * safe to apply to all versions, with the limitation of odd ratios.
330 * If RCW has disabled DDR PLL, we have to apply this workaround,
331 * otherwise DDR will not work.
332 */
333 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
334 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
335 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
336 /* check if RCW sets ratio to 0, required by this workaround */
337 if (ddr_pll_ratio != 0)
338 return;
339 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
340 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
341 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
342 /* check if reserved bits have the desired ratio */
343 if (ddr_pll_ratio == 0) {
344 printf("Error: Unknown DDR PLL ratio!\n");
345 return;
346 }
347 ddr_pll_ratio >>= 1;
348
349 setbits_be32(plldadcr1, 0x02000001);
350 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
351 setbits_be32(plldadcr2, 0x02000001);
352 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
353 setbits_be32(plldadcr3, 0x02000001);
354 #endif
355 #endif
356 setbits_be32(dpdovrcr4, 0xe0000000);
357 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
358 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
359 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
360 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
361 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
362 #endif
363 #endif
364 udelay(100);
365 clrbits_be32(plldadcr1, 0x02000001);
366 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
367 clrbits_be32(plldadcr2, 0x02000001);
368 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
369 clrbits_be32(plldadcr3, 0x02000001);
370 #endif
371 #endif
372 clrbits_be32(dpdovrcr4, 0xe0000000);
373 }
374 #endif
375
cpu_init_f(void)376 ulong cpu_init_f(void)
377 {
378 extern void m8560_cpm_reset (void);
379 #ifdef CFG_SYS_DCSRBAR_PHYS
380 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
381 #endif
382 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
383 struct law_entry law;
384 #endif
385 #ifdef CONFIG_ARCH_MPC8548
386 ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
387 uint svr = get_svr();
388
389 /*
390 * CPU2 errata workaround: A core hang possible while executing
391 * a msync instruction and a snoopable transaction from an I/O
392 * master tagged to make quick forward progress is present.
393 * Fixed in silicon rev 2.1.
394 */
395 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
396 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
397 #endif
398
399 disable_tlb(14);
400 disable_tlb(15);
401
402 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
403 /* Disable the LAW created for NOR flash by the PBI commands */
404 law = find_law(CFG_SYS_PBI_FLASH_BASE);
405 if (law.index != -1)
406 disable_law(law.index);
407
408 #if defined(CONFIG_SYS_CPC_REINIT_F)
409 disable_cpc_sram();
410 #endif
411 #endif
412
413 init_early_memctl_regs();
414
415 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
416 /* Config QE ioports */
417 config_qe_ioports();
418 #endif
419
420 #if defined(CONFIG_FSL_DMA)
421 dma_init();
422 #endif
423 #ifdef CONFIG_FSL_CORENET
424 corenet_tb_init();
425 #endif
426 init_used_tlb_cams();
427
428 /* Invalidate the CPC before DDR gets enabled */
429 invalidate_cpc();
430
431 #ifdef CFG_SYS_DCSRBAR_PHYS
432 /* set DCSRCR so that DCSR space is 1G */
433 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
434 in_be32(&gur->dcsrcr);
435 #endif
436
437 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
438 fsl_erratum_a007212_workaround();
439 #endif
440
441 return 0;
442 }
443
444 /* Implement a dummy function for those platforms w/o SERDES */
__fsl_serdes__init(void)445 static void __fsl_serdes__init(void)
446 {
447 return;
448 }
449 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
450
451 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
enable_cluster_l2(void)452 int enable_cluster_l2(void)
453 {
454 int i = 0;
455 u32 cluster, svr = get_svr();
456 ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
457 struct ccsr_cluster_l2 __iomem *l2cache;
458
459 /* only the L2 of first cluster should be enabled as expected on T4080,
460 * but there is no EOC in the first cluster as HW sake, so return here
461 * to skip enabling L2 cache of the 2nd cluster.
462 */
463 if (SVR_SOC_VER(svr) == SVR_T4080)
464 return 0;
465
466 cluster = in_be32(&gur->tp_cluster[i].lower);
467 if (cluster & TP_CLUSTER_EOC)
468 return 0;
469
470 /* The first cache has already been set up, so skip it */
471 i++;
472
473 /* Look through the remaining clusters, and set up their caches */
474 do {
475 int j, cluster_valid = 0;
476
477 l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
478
479 cluster = in_be32(&gur->tp_cluster[i].lower);
480
481 /* check that at least one core/accel is enabled in cluster */
482 for (j = 0; j < 4; j++) {
483 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
484 u32 type = in_be32(&gur->tp_ityp[idx]);
485
486 if ((type & TP_ITYP_AV) &&
487 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
488 cluster_valid = 1;
489 }
490
491 if (cluster_valid) {
492 /* set stash ID to (cluster) * 2 + 32 + 1 */
493 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
494
495 printf("enable l2 for cluster %d %p\n", i, l2cache);
496
497 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
498 while ((in_be32(&l2cache->l2csr0)
499 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
500 ;
501 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
502 }
503 i++;
504 } while (!(cluster & TP_CLUSTER_EOC));
505
506 return 0;
507 }
508 #endif
509
510 /*
511 * Initialize L2 as cache.
512 */
l2cache_init(void)513 int l2cache_init(void)
514 {
515 __maybe_unused u32 svr = get_svr();
516 #ifdef CONFIG_L2_CACHE
517 ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
518 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
519 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
520 #endif
521
522 puts ("L2: ");
523
524 #if defined(CONFIG_L2_CACHE)
525 volatile uint cache_ctl;
526 uint ver;
527 u32 l2siz_field;
528
529 ver = SVR_SOC_VER(svr);
530
531 asm("msync;isync");
532 cache_ctl = l2cache->l2ctl;
533
534 #if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
535 if (cache_ctl & MPC85xx_L2CTL_L2E) {
536 /* Clear L2 SRAM memory-mapped base address */
537 out_be32(&l2cache->l2srbar0, 0x0);
538 out_be32(&l2cache->l2srbar1, 0x0);
539
540 /* set MBECCDIS=0, SBECCDIS=0 */
541 clrbits_be32(&l2cache->l2errdis,
542 (MPC85xx_L2ERRDIS_MBECC |
543 MPC85xx_L2ERRDIS_SBECC));
544
545 /* set L2E=0, L2SRAM=0 */
546 clrbits_be32(&l2cache->l2ctl,
547 (MPC85xx_L2CTL_L2E |
548 MPC85xx_L2CTL_L2SRAM_ENTIRE));
549 }
550 #endif
551
552 l2siz_field = (cache_ctl >> 28) & 0x3;
553
554 switch (l2siz_field) {
555 case 0x0:
556 printf(" unknown size (0x%08x)\n", cache_ctl);
557 return -1;
558 break;
559 case 0x1:
560 if (ver == SVR_8540 || ver == SVR_8560 ||
561 ver == SVR_8541 || ver == SVR_8555) {
562 puts("128 KiB ");
563 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
564 cache_ctl = 0xc4000000;
565 } else {
566 puts("256 KiB ");
567 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
568 }
569 break;
570 case 0x2:
571 if (ver == SVR_8540 || ver == SVR_8560 ||
572 ver == SVR_8541 || ver == SVR_8555) {
573 puts("256 KiB ");
574 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
575 cache_ctl = 0xc8000000;
576 } else {
577 puts("512 KiB ");
578 /* set L2E=1, L2I=1, & L2SRAM=0 */
579 cache_ctl = 0xc0000000;
580 }
581 break;
582 case 0x3:
583 puts("1024 KiB ");
584 /* set L2E=1, L2I=1, & L2SRAM=0 */
585 cache_ctl = 0xc0000000;
586 break;
587 }
588
589 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
590 puts("already enabled");
591 #if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
592 u32 l2srbar = l2cache->l2srbar0;
593 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
594 && l2srbar >= CFG_SYS_FLASH_BASE) {
595 l2srbar = CFG_SYS_INIT_L2_ADDR;
596 l2cache->l2srbar0 = l2srbar;
597 printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR);
598 }
599 #endif /* CFG_SYS_INIT_L2_ADDR */
600 puts("\n");
601 } else {
602 asm("msync;isync");
603 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
604 asm("msync;isync");
605 puts("enabled\n");
606 }
607 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
608 if (SVR_SOC_VER(svr) == SVR_P2040) {
609 puts("N/A\n");
610 goto skip_l2;
611 }
612
613 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
614
615 /* invalidate the L2 cache */
616 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
617 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
618 ;
619
620 #ifdef CONFIG_SYS_CACHE_STASHING
621 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
622 mtspr(SPRN_L2CSR1, (32 + 1));
623 #endif
624
625 /* enable the cache */
626 mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
627
628 if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
629 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
630 ;
631 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
632 }
633
634 skip_l2:
635 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
636 if (l2cache->l2csr0 & L2CSR0_L2E)
637 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
638 " enabled\n");
639
640 enable_cluster_l2();
641 #else
642 puts("disabled\n");
643 #endif
644
645 return 0;
646 }
647
648 /*
649 *
650 * The newer 8548, etc, parts have twice as much cache, but
651 * use the same bit-encoding as the older 8555, etc, parts.
652 *
653 */
cpu_init_r(void)654 int cpu_init_r(void)
655 {
656 __maybe_unused u32 svr = get_svr();
657 #ifdef CFG_SYS_LBC_LCRR
658 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
659 #endif
660 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
661 extern int spin_table_compat;
662 const char *spin;
663 #endif
664 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
665 ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
666 #endif
667 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
668 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
669 /*
670 * CPU22 and NMG_CPU_A011 share the same workaround.
671 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
672 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
673 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
674 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
675 * be disabled by hwconfig with syntax:
676 *
677 * fsl_cpu_a011:disable
678 */
679 extern int enable_cpu_a011_workaround;
680 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
681 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
682 #else
683 char buffer[HWCONFIG_BUFFER_SIZE];
684 char *buf = NULL;
685 int n, res;
686
687 n = env_get_f("hwconfig", buffer, sizeof(buffer));
688 if (n > 0)
689 buf = buffer;
690
691 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
692 if (res > 0) {
693 enable_cpu_a011_workaround = 0;
694 } else {
695 if (n >= HWCONFIG_BUFFER_SIZE) {
696 printf("fsl_cpu_a011 was not found. hwconfig variable "
697 "may be too long\n");
698 }
699 enable_cpu_a011_workaround =
700 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
701 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
702 }
703 #endif
704 if (enable_cpu_a011_workaround) {
705 flush_dcache();
706 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
707 sync();
708 }
709 #endif
710
711 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
712 flush_dcache();
713 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
714 sync();
715 #endif
716
717 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
718 /*
719 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
720 * in write shadow mode. Checking DCWS before setting SPR 976.
721 */
722 if (mfspr(L1CSR2) & L1CSR2_DCWS)
723 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
724 #endif
725
726 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
727 spin = env_get("spin_table_compat");
728 if (spin && (*spin == 'n'))
729 spin_table_compat = 0;
730 else
731 spin_table_compat = 1;
732 #endif
733
734 #ifdef CONFIG_FSL_CORENET
735 set_liodns();
736 #ifdef CONFIG_SYS_DPAA_QBMAN
737 setup_qbman_portals();
738 #endif
739 #endif
740
741 l2cache_init();
742 #if defined(CONFIG_RAMBOOT_PBL)
743 disable_cpc_sram();
744 #endif
745 enable_cpc();
746 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
747 enable_tdm_law();
748 #endif
749
750 #ifndef CONFIG_SYS_FSL_NO_SERDES
751 /* needs to be in ram since code uses global static vars */
752 fsl_serdes_init();
753 #endif
754
755 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
756 #define MCFGR_AXIPIPE 0x000000f0
757 if (IS_SVR_REV(svr, 1, 0))
758 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
759 #endif
760
761 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
762 if (IS_SVR_REV(svr, 1, 0)) {
763 int i;
764 __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
765
766 for (i = 0; i < 12; i++) {
767 p += i + (i > 5 ? 11 : 0);
768 out_be32(p, 0x2);
769 }
770 p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
771 out_be32(p, 0x34);
772 }
773 #endif
774
775 #ifdef CONFIG_SYS_SRIO
776 srio_init();
777 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
778 char *s = env_get("bootmaster");
779 if (s) {
780 if (!strcmp(s, "SRIO1")) {
781 srio_boot_master(1);
782 srio_boot_master_release_slave(1);
783 }
784 if (!strcmp(s, "SRIO2")) {
785 srio_boot_master(2);
786 srio_boot_master_release_slave(2);
787 }
788 }
789 #endif
790 #endif
791
792 #if defined(CONFIG_MP)
793 setup_mp();
794 #endif
795
796 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
797 {
798 if (SVR_MAJ(svr) < 3) {
799 void *p;
800 p = (void *)CFG_SYS_DCSRBAR + 0x20520;
801 setbits_be32(p, 1 << (31 - 14));
802 }
803 }
804 #endif
805
806 #ifdef CFG_SYS_LBC_LCRR
807 /*
808 * Modify the CLKDIV field of LCRR register to improve the writing
809 * speed for NOR flash.
810 */
811 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR);
812 __raw_readl(&lbc->lcrr);
813 isync();
814 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
815 udelay(100);
816 #endif
817 #endif
818
819 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
820 {
821 struct ccsr_usb_phy __iomem *usb_phy1 =
822 (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
823 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
824 if (has_erratum_a006261())
825 fsl_erratum_a006261_workaround(usb_phy1);
826 #endif
827 out_be32(&usb_phy1->usb_enable_override,
828 CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
829 }
830 #endif
831 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
832 {
833 struct ccsr_usb_phy __iomem *usb_phy2 =
834 (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
835 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
836 if (has_erratum_a006261())
837 fsl_erratum_a006261_workaround(usb_phy2);
838 #endif
839 out_be32(&usb_phy2->usb_enable_override,
840 CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
841 }
842 #endif
843
844 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
845 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
846 * multi-bit ECC errors which has impact on performance, so software
847 * should disable all ECC reporting from USB1 and USB2.
848 */
849 if (IS_SVR_REV(get_svr(), 1, 0)) {
850 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
851 (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET);
852 setbits_be32(&dcfg->ecccr1,
853 (DCSR_DCFG_ECC_DISABLE_USB1 |
854 DCSR_DCFG_ECC_DISABLE_USB2));
855 }
856 #endif
857
858 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
859 struct ccsr_usb_phy __iomem *usb_phy =
860 (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
861 setbits_be32(&usb_phy->pllprg[1],
862 CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
863 CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
864 CFG_SYS_FSL_USB_PLLPRG2_MFI |
865 CFG_SYS_FSL_USB_PLLPRG2_PLL_EN);
866 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
867 usb_single_source_clk_configure(usb_phy);
868 #endif
869 setbits_be32(&usb_phy->port1.ctrl,
870 CFG_SYS_FSL_USB_CTRL_PHY_EN);
871 setbits_be32(&usb_phy->port1.drvvbuscfg,
872 CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
873 setbits_be32(&usb_phy->port1.pwrfltcfg,
874 CFG_SYS_FSL_USB_PWRFLT_CR_EN);
875 setbits_be32(&usb_phy->port2.ctrl,
876 CFG_SYS_FSL_USB_CTRL_PHY_EN);
877 setbits_be32(&usb_phy->port2.drvvbuscfg,
878 CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
879 setbits_be32(&usb_phy->port2.pwrfltcfg,
880 CFG_SYS_FSL_USB_PWRFLT_CR_EN);
881
882 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
883 if (has_erratum_a006261())
884 fsl_erratum_a006261_workaround(usb_phy);
885 #endif
886
887 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
888
889 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
890 erratum_a009942_check_cpo();
891 #endif
892
893 #ifdef CONFIG_FMAN_ENET
894 #ifndef CONFIG_DM_ETH
895 fman_enet_init();
896 #endif
897 #endif
898
899 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
900 if (pamu_init() < 0)
901 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
902 #endif
903
904 #ifdef CONFIG_FSL_CAAM
905 #if defined(CONFIG_ARCH_C29X)
906 if ((SVR_SOC_VER(svr) == SVR_C292) ||
907 (SVR_SOC_VER(svr) == SVR_C293))
908 sec_init_idx(1);
909
910 if (SVR_SOC_VER(svr) == SVR_C293)
911 sec_init_idx(2);
912 #endif
913 #endif
914
915 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
916 /*
917 * For P1022/1013 Rev1.0 silicon, after power on SATA host
918 * controller is configured in legacy mode instead of the
919 * expected enterprise mode. Software needs to clear bit[28]
920 * of HControl register to change to enterprise mode from
921 * legacy mode. We assume that the controller is offline.
922 */
923 if (IS_SVR_REV(svr, 1, 0) &&
924 ((SVR_SOC_VER(svr) == SVR_P1022) ||
925 (SVR_SOC_VER(svr) == SVR_P1013))) {
926 fsl_sata_reg_t *reg;
927
928 /* first SATA controller */
929 reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
930 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
931
932 /* second SATA controller */
933 reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
934 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
935 }
936 #endif
937
938 init_used_tlb_cams();
939
940 return 0;
941 }
942
arch_preboot_os(void)943 void arch_preboot_os(void)
944 {
945 u32 msr;
946
947 /*
948 * We are changing interrupt offsets and are about to boot the OS so
949 * we need to make sure we disable all async interrupts. EE is already
950 * disabled by the time we get called.
951 */
952 msr = mfmsr();
953 msr &= ~(MSR_ME|MSR_CE);
954 mtmsr(msr);
955 }
956
cpu_secondary_init_r(void)957 int cpu_secondary_init_r(void)
958 {
959 #ifdef CONFIG_QE
960 #ifdef CONFIG_U_QE
961 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
962 #else
963 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
964 #endif
965
966 qe_init(qe_base);
967 qe_reset();
968 #endif
969
970 return 0;
971 }
972
973 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)974 int board_late_init(void)
975 {
976 #ifdef CONFIG_CHAIN_OF_TRUST
977 fsl_setenv_chain_of_trust();
978 #endif
979
980 return 0;
981 }
982 #endif
983