1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#include "am33xx.dtsi"
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	model = "Phytec AM335x phyCORE";
12	compatible = "phytec,am335x-phycore-som", "ti,am33xx";
13
14	aliases {
15		rtc0 = &i2c_rtc;
16		rtc1 = &rtc;
17	};
18
19	cpus {
20		cpu@0 {
21			cpu0-supply = <&vdd1_reg>;
22		};
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x80000000 0x10000000>; /* 256 MB */
28	};
29
30	vcc5v: fixedregulator0 {
31		compatible = "regulator-fixed";
32		regulator-name = "vcc5v";
33		regulator-min-microvolt = <5000000>;
34		regulator-max-microvolt = <5000000>;
35		regulator-boot-on;
36		regulator-always-on;
37	};
38};
39
40/* Crypto Module */
41&aes {
42	status = "okay";
43};
44
45&sham {
46	status = "okay";
47};
48
49/* Ethernet */
50&am33xx_pinmux {
51	ethernet0_pins: pinmux_ethernet0 {
52		pinctrl-single,pins = <
53			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
54			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
55			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
56			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
57			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
58			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
59			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
60			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
61		>;
62	};
63
64	mdio_pins: pinmux_mdio {
65		pinctrl-single,pins = <
66			/* MDIO */
67			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
68			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
69		>;
70	};
71};
72
73&cpsw_emac0 {
74	phy-handle = <&phy0>;
75	phy-mode = "rmii";
76	dual_emac_res_vlan = <1>;
77};
78
79&davinci_mdio {
80	pinctrl-names = "default";
81	pinctrl-0 = <&mdio_pins>;
82	status = "okay";
83
84	phy0: ethernet-phy@0 {
85		reg = <0>;
86	};
87};
88
89&mac {
90	slaves = <1>;
91	pinctrl-names = "default";
92	pinctrl-0 = <&ethernet0_pins>;
93	status = "okay";
94};
95
96/* I2C Busses */
97&am33xx_pinmux {
98	i2c0_pins: pinmux_i2c0 {
99		pinctrl-single,pins = <
100			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
101			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
102		>;
103	};
104};
105
106&i2c0 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&i2c0_pins>;
109	clock-frequency = <400000>;
110	status = "okay";
111
112	tps: pmic@2d {
113		reg = <0x2d>;
114	};
115
116	i2c_tmp102: temp@4b {
117		compatible = "ti,tmp102";
118		reg = <0x4b>;
119		status = "disabled";
120	};
121
122	i2c_eeprom: eeprom@52 {
123		compatible = "atmel,24c32";
124		pagesize = <32>;
125		reg = <0x52>;
126		status = "disabled";
127	};
128
129	i2c_rtc: rtc@68 {
130		compatible = "microcrystal,rv4162";
131		reg = <0x68>;
132		status = "disabled";
133	};
134};
135
136/* NAND memory */
137&am33xx_pinmux {
138		nandflash_pins: pinmux_nandflash {
139			pinctrl-single,pins = <
140			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
141			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
142			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
143			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
144			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
145			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
146			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
147			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
148			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
149			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
150			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
151			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
152			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
153			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
154		>;
155	};
156};
157
158&elm {
159	status = "okay";
160};
161
162&gpmc {
163	status = "okay";
164	pinctrl-names = "default";
165	pinctrl-0 = <&nandflash_pins>;
166	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
167	nandflash: nand@0,0 {
168		compatible = "ti,omap2-nand";
169		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
170		interrupt-parent = <&gpmc>;
171		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
172			     <1 IRQ_TYPE_NONE>;	/* termcount */
173		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
174		nand-bus-width = <8>;
175		ti,nand-ecc-opt = "bch8";
176		gpmc,device-nand = "true";
177		gpmc,device-width = <1>;
178		gpmc,sync-clk-ps = <0>;
179		gpmc,cs-on-ns = <0>;
180		gpmc,cs-rd-off-ns = <30>;
181		gpmc,cs-wr-off-ns = <30>;
182		gpmc,adv-on-ns = <0>;
183		gpmc,adv-rd-off-ns = <30>;
184		gpmc,adv-wr-off-ns = <30>;
185		gpmc,we-on-ns = <0>;
186		gpmc,we-off-ns = <20>;
187		gpmc,oe-on-ns = <10>;
188		gpmc,oe-off-ns = <30>;
189		gpmc,access-ns = <30>;
190		gpmc,rd-cycle-ns = <30>;
191		gpmc,wr-cycle-ns = <30>;
192		gpmc,bus-turnaround-ns = <0>;
193		gpmc,cycle2cycle-delay-ns = <50>;
194		gpmc,cycle2cycle-diffcsen;
195		gpmc,clk-activation-ns = <0>;
196		gpmc,wr-access-ns = <30>;
197		gpmc,wr-data-mux-bus-ns = <0>;
198
199		ti,elm-id = <&elm>;
200
201		#address-cells = <1>;
202		#size-cells = <1>;
203	};
204};
205
206/* Power */
207#include "tps65910.dtsi"
208
209&tps {
210	vcc1-supply = <&vcc5v>;
211	vcc2-supply = <&vcc5v>;
212	vcc3-supply = <&vcc5v>;
213	vcc4-supply = <&vcc5v>;
214	vcc5-supply = <&vcc5v>;
215	vcc6-supply = <&vcc5v>;
216	vcc7-supply = <&vcc5v>;
217	vccio-supply = <&vcc5v>;
218
219	regulators {
220		vrtc_reg: regulator@0 {
221			regulator-always-on;
222		};
223
224		vio_reg: regulator@1 {
225			regulator-always-on;
226		};
227
228		vdd1_reg: regulator@2 {
229			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
230			regulator-name = "vdd_mpu";
231			regulator-min-microvolt = <912500>;
232			regulator-max-microvolt = <1378000>;
233			regulator-boot-on;
234			regulator-always-on;
235		};
236
237		vdd2_reg: regulator@3 {
238			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
239			regulator-name = "vdd_core";
240			regulator-min-microvolt = <912500>;
241			regulator-max-microvolt = <1150000>;
242			regulator-boot-on;
243			regulator-always-on;
244		};
245
246		vdd3_reg: regulator@4 {
247			regulator-always-on;
248		};
249
250		vdig1_reg: regulator@5 {
251			regulator-name = "vdig1_1p8v";
252			regulator-min-microvolt = <1800000>;
253			regulator-max-microvolt = <1800000>;
254		};
255
256		vdig2_reg: regulator@6 {
257			regulator-always-on;
258		};
259
260		vpll_reg: regulator@7 {
261			regulator-always-on;
262		};
263
264		vdac_reg: regulator@8 {
265			regulator-always-on;
266		};
267
268		vaux1_reg: regulator@9 {
269			regulator-always-on;
270		};
271
272		vaux2_reg: regulator@10 {
273			regulator-always-on;
274		};
275
276		vaux33_reg: regulator@11 {
277			regulator-always-on;
278		};
279
280		vmmc_reg: regulator@12 {
281			regulator-min-microvolt = <3300000>;
282			regulator-max-microvolt = <3300000>;
283			regulator-always-on;
284		};
285	};
286};
287
288/* SPI Busses */
289&am33xx_pinmux {
290	spi0_pins: pinmux_spi0 {
291		pinctrl-single,pins = <
292			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
293			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
294			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
295			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
296		>;
297	};
298};
299
300&spi0 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&spi0_pins>;
303	status = "okay";
304
305	serial_flash: flash@0 {
306		compatible = "jedec,spi-nor";
307		spi-max-frequency = <48000000>;
308		reg = <0x0>;
309		m25p,fast-read;
310		status = "disabled";
311		#address-cells = <1>;
312		#size-cells = <1>;
313	};
314};
315